Commit 35276bb9 authored by Vraliens's avatar Vraliens Committed by Grzegorz Daniluk

Add CUTE-WR-DP board support by Tsinghua University

parent a1602aaf
files = [
"cute_reset_gen.vhd",
"wr_cute_pkg.vhd",
"xwrc_board_cute.vhd",
]
modules = {
"local" : [
"../common",
]
}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_reset_gen is
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end cute_reset_gen;
architecture behavioral of cute_reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal powerup_n : std_logic := '0';
signal button_synced_n : std_logic;
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component;
begin -- behavioral
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n;
end behavioral;
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CUTE package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_cute_pkg.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Company : Tsinghua Univ. (DEP)
-- Created : 2018-07-14
-- Last update: 2018-07-14
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- cute special
g_sfp0_enable : boolean:= true;
g_sfp1_enable : boolean:= false;
g_multiboot_enable : boolean:= false);
port (
rst_n_i : in std_logic;
clk_20m_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
clk_sfp0_i : in std_logic :='0';
clk_sfp1_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic;
sfp0_rxn_i : in std_logic;
sfp0_det_i : in std_logic;
sfp0_scl_i : in std_logic;
sfp0_scl_o : out std_logic;
sfp0_sda_i : in std_logic;
sfp0_sda_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic;
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic;
sfp0_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp0_rx_rbclk_o : out std_logic;
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic;
sfp1_rxn_i : in std_logic;
sfp1_det_i : in std_logic;
sfp1_scl_i : in std_logic;
sfp1_scl_o : out std_logic;
sfp1_sda_i : in std_logic;
sfp1_sda_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic;
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic;
sfp1_refclk_sel_i : in std_logic_vector(2 downto 0):="110";
sfp1_rx_rbclk_o : out std_logic;
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
This diff is collapsed.
files = [
"spec_serial_dac_arb.vhd",
"spec_serial_dac.vhd"
"spec_serial_dac.vhd",
"cute_serial_dac_arb.vhd",
"cute_serial_dac.vhd"
]
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-- 2012-10-15 2.0 pwb Modified for AD5663R of CUTE-WR
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cute_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic
);
end cute_serial_dac;
architecture syn of cute_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
begin
-- Modified by Weibin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(2); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(3); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(4); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(5); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(6); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(7); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(8); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(9); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (divider'high downto 1 => '0') & '1';
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (divider'high downto 1 => '0') & '1';
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (divider'high downto 1 => '0') & '1';
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= cmd_i;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 1 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
dac_sync_n_o <= not sendingData;
dac_sclk_o <= iDacClk;
end syn;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end cute_serial_dac_arb;
architecture behavioral of cute_serial_dac_arb is
component cute_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
signal dac_cmd : std_logic_vector(g_num_extra_bits-1 downto 0);
signal init_cnt : unsigned(7 downto 0);
type t_state is (INIT, ENABLE_INT_REF, WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
dac_ldac_n_o <= '0';
U_DAC : cute_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cmd_i => dac_cmd,
load_i => dac_load,
sclk_divsel_i => "001",
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
dac_sync_n_o => dac_sync_n_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
init_cnt <= (others => '0');
state <= INIT;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when INIT =>
if init_cnt(6) = '1' then
state <= ENABLE_INT_REF;
else
init_cnt <= init_cnt +1;
end if;
when ENABLE_INT_REF =>
dac_cmd <= "00111000";
dac_data <= (dac_data'high downto 1 => '0') & '0'; -- internal reference setup
dac_load <= '1';
state <= LOAD_DAC;
when WAIT_DATA =>
if(d1_ready = '1') then
dac_data <= d1;
dac_cmd <= "00011001"; -- write and update DAC B
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_data <= d2;
dac_cmd <= "00011000"; -- write and update DAC A
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
This diff is collapsed.
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "csg324"
syn_top = "cute_wr_ref_top"
syn_project = "cute_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/cute_ref_design/"}
This diff is collapsed.
fetchto = "../../ip_cores"
files = [
"cute_core_ref_top.vhd",
"cute_wr_ref_top.vhd",
"cute_wr_ref_top.ucf",
]
modules = {
"local" : [
"../../",
"../../board/cute",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
This diff is collapsed.
config vccaux = 3.3;
# bank 0
#net "clk1_m2c_p" loc = b3;net "clk1_m2c_p" iostandard = lvds_33;
#net "clk1_m2c_n" loc = a3;net "clk1_m2c_n" iostandard = lvds_33;
#net "la03_p" loc = e6;net "la03_p" iostandard = lvds_33;
#net "la03_n" loc = f7;net "la03_n" iostandard = lvds_33;
#net "la01_cc_p" loc = g8;net "la01_cc_p" iostandard = lvds_33;
#net "la01_cc_n" loc = e8;net "la01_cc_n" iostandard = lvds_33;
#net "la20_p" loc = g9;net "la20_p" iostandard = lvds_33;
#net "la20_n" loc = g11;net "la20_n" iostandard = lvds_33;
#net "la30_p" loc = c15;net "la30_p" iostandard = lvds_33;
#net "la30_n" loc = a15;net "la30_n" iostandard = lvds_33;
#net "la29_p" loc = b16;net "la29_p" iostandard = lvds_33;
#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
net "fpga_clk_p" loc = f12;net "fpga_clk_p" iostandard = lvds_33;
net "fpga_clk_n" loc = e12;net "fpga_clk_n" iostandard = lvds_33;
# bank 1
net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
net "usr_led1" loc = e18;net "usr_led1" iostandard = lvcmos33;
net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
#net "sfp1_tx_los" loc = f18;net "sfp1_tx_los" iostandard = lvcmos33;
#net "sfp1_tx_fault" loc = h16;net "sfp1_tx_fault" iostandard = lvcmos33;
#net "sfp1_det" loc = g16;net "sfp1_det" iostandard = lvcmos33;
#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
#net "la32_p" loc = p17;net "la32_p" iostandard = lvds_33;
#net "la32_n" loc = p18;net "la32_n" iostandard = lvds_33;
#net "la33_p" loc = t17;net "la33_p" iostandard = lvds_33;
#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
# bank 2
net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
net "flash_mosi_o" loc = t13;net "flash_mosi_o" iostandard = lvcmos33;
net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
#net "la28_p" loc = u16;net "la28_p" iostandard = lvds_33;
#net "la28_n" loc = v16;net "la28_n" iostandard = lvds_33;
#net "la25_p" loc = u15;net "la25_p" iostandard = lvds_33;
#net "la25_n" loc = v15;net "la25_n" iostandard = lvds_33;
#net "la26_p" loc = t14;net "la26_p" iostandard = lvds_33;
#net "la26_n" loc = v14;net "la26_n" iostandard = lvds_33;
#net "la21_p" loc = u13;net "la21_p" iostandard = lvds_33;
#net "la21_n" loc = v13;net "la21_n" iostandard = lvds_33;
#net "la27_p" loc = m11;net "la27_p" iostandard = lvds_33;
#net "la27_n" loc = n11;net "la27_n" iostandard = lvds_33;