Commit ed3204cc authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

platform_xilinx: separate locked output for sys_pll

parent 7c8ec4b7
......@@ -173,7 +173,7 @@ package wr_cute_pkg is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
pll_locked_o : out std_logic;
pll_aux_locked_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
......
......@@ -275,7 +275,7 @@ entity xwrc_board_cute is
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o: out std_logic;
pll_locked_o : out std_logic;
pll_aux_locked_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
......@@ -426,6 +426,7 @@ begin -- architecture struct
clk_20m_o => clk_pll_20m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
pll_aux_locked_o => pll_aux_locked_o,
clk_10m_ext_o => clk_10m_ext,
phy8_o => phy8_to_wrc,
phy8_i => phy8_from_wrc,
......@@ -674,7 +675,6 @@ begin -- architecture struct
link_ok_o => link_ok_o);
tm_time_valid_o <= tm_time_valid;
pll_locked_o <= pll_locked;
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
......
......@@ -3,6 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"oserdes_4_to_1",
"oserdes_4_to_1.vhd",
"pulse_stamper.vhd" ]
......@@ -312,7 +312,7 @@ begin
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_csync,
pll_locked_o => pll_locked,
pll_aux_locked_o => pll_locked,
link_ok_o => usr_led2);
cnx_slave_in <= cnx_master_out;
......
......@@ -325,7 +325,7 @@ begin
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_csync,
pll_locked_o => pll_locked,
pll_aux_locked_o => pll_locked,
link_ok_o => usr_led2);
cnx_slave_in <= cnx_master_out;
......
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