- 15 Sep, 2020 28 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
wr_si57x_interface: latch the current RFREQ value before writing it to the device (prevents changes of the RFREQ while I2C is still busy)
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
wr_board_pkg: declare eb_ethernet_slave as a component so that compiler doesn't complain when EB repo is not included
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 14 Sep, 2020 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 13 May, 2020 1 commit
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Tomasz Wlostowski authored
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- 29 Apr, 2020 1 commit
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Maciej Lipinski authored
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- 25 Apr, 2020 1 commit
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Maciej Lipinski authored
New statistics data was added to diag/snmp array. To ensure backward-comapatibity between MIB versions, this new data needs to be added at the end. Thus, now we need to inject dbg_word and magic number in the middle. The diag_ver is not bumped because the change is backward-compatible.
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- 23 Apr, 2020 1 commit
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Maciej Lipinski authored
This was previously implemented but got lost when the fixed latency instreamers was re-done. The idea is to compensate for internal delays, so that the tx/rx_valid signals are as close to the configured latency as possible. Corrected simulation accordingly: the simulation also corrected for delays.
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- 22 Apr, 2020 1 commit
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Maciej Lipinski authored
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- 21 Apr, 2020 1 commit
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Maciej Lipinski authored
For simulation, the second duration is forced to be shorter with the generic g_sim_cycle_counter_range. The problem is that the tai/cycle counters are still counting full seconds, the trick was done only when calculating the delay in function f_cycles_counter_range() in fixed_latency_ts_match.vhd. This worked fine unless the timestamps were at the edge of the "shorter" second and fixed-latency was enabled. In such case, it happened that the time of releasing data from streamers was calcualted for TAI+1, yet TAI was incremented after the "true" second, not the shorter one. So, the simulation was stuck. To avoid messing up with PPS gen in which the tai/cycles are generated, for simulation the tai/cycle values are overriden in the xwr_streamer top module. This "alternative" TAI time is counted from the time when time_valid goes HIGH. This solution should work for streamers, provided that tx/rx instances have the time_valid go HIGH more or less at the same time. As far as I can tell, this is usually the case.
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- 09 Apr, 2020 1 commit
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Maciej Lipinski authored
oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/ that include generic modules. This prevented the Altera-based design from building. Ultimately, the module needs to be moved to some more appropriate place, possibly to general-cores/platform/xilinx. To be decided. A temporary solution is to have it in board/cute, since it is only used by in the xwrc_board_cute.
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- 08 Apr, 2020 1 commit
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Grzegorz Daniluk authored
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- 07 Apr, 2020 1 commit
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Maciej Lipinski authored
It seems that pll_aux_locked is in clk_sys clock domain. When synthesising cute for BTrain I had timing errors in the 10MHz generation process. This commit fixes the timing issues.
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