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White Rabbit core collection
Commit a72a4223 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tomasz Wlostowski
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board/s[v,p]ec: added DMTD clock output

parent be42d527
Pipeline #234 failed with stages
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      board/spec/wr_spec_pkg.vhd
      View file @ a72a4223
      ......@@ -77,6 +77,7 @@ package wr_spec_pkg is
      pps_ext_i : in std_logic := '0';
      clk_sys_62m5_o : out std_logic;
      clk_ref_125m_o : out std_logic;
      clk_dmtd_125m_o : out std_logic;
      clk_pll_aux_o : out std_logic_vector(3 downto 0);
      rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
      rst_sys_62m5_n_o : out std_logic;
      ......
      board/spec/xwrc_board_spec.vhd
      View file @ a72a4223
      ......@@ -110,6 +110,8 @@ entity xwrc_board_spec is
      clk_ref_125m_o : out std_logic;
      -- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
      clk_pll_aux_o : out std_logic_vector(3 downto 0);
      -- 125.x MHz DDMTD clock
      clk_dmtd_125m_o : out std_logic;
      -- active low reset outputs, synchronous to clk_pll_aux_o clocks
      rst_pll_aux_n_o : out std_logic_vector(3 downto 0);
      -- active low reset outputs, synchronous to 62m5 and 125m clocks
      ......@@ -551,4 +553,6 @@ begin -- architecture struct
      onewire_in(0) <= onewire_i;
      onewire_in(1) <= '1';
      clk_dmtd_125m_o <= clk_pll_dmtd;
      end architecture struct;
      board/svec/wr_svec_pkg.vhd
      View file @ a72a4223
      ......@@ -7,7 +7,7 @@
      -- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2017-02-16
      -- Last update: 2019-04-23
      -- Last update: 2019-09-25
      -- Standard : VHDL'93
      -------------------------------------------------------------------------------
      -- Copyright (c) 2017 CERN
      ......@@ -73,6 +73,7 @@ package wr_svec_pkg is
      clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
      clk_10m_ext_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      clk_dmtd_125m_o : out std_logic;
      clk_sys_62m5_o : out std_logic;
      clk_ref_125m_o : out std_logic;
      clk_pll_aux_o : out std_logic_vector(3 downto 0);
      ......
      board/svec/xwrc_board_svec.vhd
      View file @ a72a4223
      ......@@ -7,7 +7,7 @@
      -- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
      -- Company : CERN (BE-CO-HT)
      -- Created : 2017-02-16
      -- Last update: 2019-04-23
      -- Last update: 2019-09-25
      -- Standard : VHDL'93
      -------------------------------------------------------------------------------
      -- Description: Top-level wrapper for WR PTP core including all the modules
      ......@@ -107,6 +107,8 @@ entity xwrc_board_svec is
      clk_sys_62m5_o : out std_logic;
      -- 125MHz ref clock output
      clk_ref_125m_o : out std_logic;
      -- 125.x MHz DDMTD clock
      clk_dmtd_125m_o : out std_logic;
      -- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
      clk_pll_aux_o : out std_logic_vector(3 downto 0);
      -- active low reset outputs, synchronous to clk_pll_aux_o clocks
      ......@@ -278,6 +280,9 @@ architecture struct of xwrc_board_svec is
      signal clk_10m_ext : std_logic;
      signal clk_pll_aux : std_logic_vector(3 downto 0);
      attribute keep : string;
      attribute keep of clk_pll_dmtd : signal is "TRUE";
      -- Reset logic
      signal areset_edge_ppulse : std_logic;
      signal rst_62m5_n : std_logic;
      ......@@ -549,4 +554,6 @@ begin -- architecture struct
      onewire_in(0) <= onewire_i;
      onewire_in(1) <= '1';
      clk_dmtd_125m_o <= clk_pll_dmtd;
      end architecture struct;
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