[CUTE] move oserdes_4_to_1 to board/cute (temporary solution)

oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/ that include generic modules. This prevented the Altera-based design from building. Ultimately, the module needs to be moved to some more appropriate place, possibly to general-cores/platform/xilinx. To be decided. A temporary solution is to have it in board/cute, since it is only used by in the xwrc_board_cute.

[CUTE] move oserdes_4_to_1 to board/cute (temporary solution)
oserdes_4_to_1.vhd is Xilinx-specific and cannot be in modules/ that include generic modules. This prevented the Altera-based design from building. Ultimately, the module needs to be moved to some more appropriate place, possibly to general-cores/platform/xilinx. To be decided. A temporary solution is to have it in board/cute, since it is only used by in the xwrc_board_cute.
c6a8b74d · Maciej Lipinski · 7ac9c72f · c6a8b74d · c6a8b74d · c6a8b74d
Commit c6a8b74d authored Apr 09, 2020 by Maciej Lipinski
Showing with 2 additions and 2 deletions

Manifest.py board/cute/Manifest.py +1 -0

oserdes_4_to_1.vhd board/cute/oserdes_4_to_1.vhd +0 -0

Manifest.py modules/timing/Manifest.py +0 -1

cute_wr_ref.xise syn/cute_ref_design/cute_wr_ref.xise +1 -1

No files found.
--- a/board/cute/Manifest.py
+++ b/board/cute/Manifest.py
 files = [
    "wr_cute_pkg.vhd",
    "xwrc_board_cute.vhd",
+    "oserdes_4_to_1.vhd",
 ]

 modules = {

--- a/modules/timing/oserdes_4_to_1.vhd
+++ b/modules/timing/oserdes_4_to_1.vhd
--- a/modules/timing/Manifest.py
+++ b/modules/timing/Manifest.py
@@ -3,7 +3,6 @@ files = ["dmtd_phase_meas.vhd",
         "multi_dmtd_with_deglitcher.vhd",
         "hpll_period_detect.vhd",
         "pulse_gen.vhd",
-         "oserdes_4_to_1.vhd",
         "pulse_stamper.vhd",
         "pulse_stamper_sync.vhd",
         "dmtd_sampler.vhd" ]
--- a/syn/cute_ref_design/cute_wr_ref.xise
+++ b/syn/cute_ref_design/cute_wr_ref.xise
@@ -1329,7 +1329,7 @@
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
    </file>
-    <file xil_pn:name="../../modules/timing/oserdes_4_to_1.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../board/cute/oserdes_4_to_1.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="390"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
    </file>