wr_gthe4_phyh_family7: last attempt to fix bitslide jumps before reverting to Xilinx's IP wrapper

24a70af3 · Tomasz Wlostowski · Grzegorz Daniluk · 6936b1f3 · 24a70af3 · 24a70af3
Commit 24a70af3 authored Jul 28, 2020 by Tomasz Wlostowski Committed by Grzegorz Daniluk Sep 15, 2020
Showing with 8 additions and 3 deletions

wr_gthe4_phy_family7.vhd .../xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7.vhd +5 -2

wr_gthe4_wrapper.vhd ...form/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd +3 -1

No files found.
--- a/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_phy_family7.vhd
@@ -183,6 +183,8 @@ architecture rtl of wr_gthe4_phy_family7 is
  signal tx_buffer_bypass_done : std_logic;
  signal rx_buffer_bypass_done : std_logic;

+  signal rx_pcs_reset : std_logic;
+
  function f_is_synthesis return boolean is
  begin
    -- synthesis translate_off
@@ -241,7 +243,7 @@ begin
   U_Bitslide : entity work.gtp_bitslide
     generic map (
       g_simulation => g_simulation,
-       g_target     => "virtex6")
+       g_target     => "ultrascale")
     port map (
       gtp_rst_i                => rst_i,
       gtp_rx_clk_i             => RXUSRCLK2,
@@ -249,7 +251,7 @@ begin
       gtp_rx_byte_is_aligned_i => RXBYTEISALIGNED,
       serdes_ready_i           => serdes_ready_rxusrclk,
       gtp_rx_slide_o           => RXSLIDE,
-       gtp_rx_cdr_rst_o         => open,
+       gtp_rx_cdr_rst_o         => rx_pcs_reset,
       bitslide_o               => rx_bitslide_o,
       synced_o                 => rx_synced);

@@ -412,6 +414,7 @@ begin
      RXBYTEISALIGNED => RXBYTEISALIGNED,
      RXCOMMADET      => RXCOMMADET,
      RXCTRL0         => RXCTRL0,
+      RXPCSRESET => rx_pcs_reset,
      rxctrl3 => rxctrl3,
      RXDATA          => RXDATA,
      RXOUTCLK        => RXOUTCLK,

--- a/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd
+++ b/platform/xilinx/wr_gtp_phy/family7-gthe4/wr_gthe4_wrapper.vhd
@@ -21,6 +21,8 @@ entity wr_gthe4_wrapper is
    TXRESETDONE    : out std_logic;
    TXPROGDIVRESET : in  std_logic;

+    RXPCSRESET : in std_logic;
+

    GTHTXN          : out std_logic;
    GTHTXP          : out std_logic;
@@ -815,7 +817,7 @@ begin
      RXOUTCLK          => RXOUTCLK,
      RXOUTCLKSEL       => "010",
      RXPCOMMAALIGNEN   => '0',
-      RXPCSRESET        => '0',
+      RXPCSRESET           => RXPCSRESET,
      RXPD              => "00",
      RXPHALIGN         => '0',
      RXPHALIGNDONE     => RXPHALIGNDONE,