This reverts commit 4b7d828e.

IRIG: update outputs on PPS

See merge request !22

Add irig slave interface

See merge request !20

Allow support of generic platforms

lpdc for virtex6 (wrs)

See merge request !19

This reverts commit 2349460e.

This reverts commit 2349460e.

WIP: Pieter fasec wrpc v5

See merge request !14

platform/xilinx/xwrc_platform_vivado.vhd: Generate direct DMTD clock using a BUFR

See merge request !15

modules/wrc_core/wrc_periph.vhd: Add reset signal to sensitivity list

See merge request !16

platform/xilinx/vivado: Fix generates of clock signals that originate from phys

See merge request !17

Remove default assignments of clock signals when g_use_default_plls = FALSE
that actually originate from the phys / transceivers and are thus independant
of said generic (signals would have multiple writers / assignements).

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>

Instead of generating the 62.5MHz DMTD clock using a process, divide an incoming
125MHz clock by 2 using a BUFR on 7Series FPGA (similarly to the Ultrascale+
path).

Signed-off-by: Frederik Pfautsch <frederik.pfautsch@missinglinkelectronics.com>