Skip to content
Snippets Groups Projects
Commit a0d54aad authored by Harvey Leicester's avatar Harvey Leicester
Browse files

add defaults to phy inputs

parent f4358704
Branches mat_ebm
1 merge request!25virtex6 phy uses rx_byte_is_aligned
Hide whitespace changes
Inline Side-by-side
modules/wr_endpoint/xwr_endpoint.vhd
+ 2
− 2
View file @ a0d54aad
......@@ -128,9 +128,9 @@ entity xwr_endpoint is
-- 2nd option is to use record-based I/Os
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
phy16_i : in t_phy_16bits_to_wrc;
phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc;
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment