platform/xilinx/xwrc_platform_vivado.vhd: Generate direct DMTD clock using a BUFR
Instead of generating the 62.5MHz DMTD clock using a process, divide an incoming 125MHz clock by 2 using a BUFR on 7Series FPGA (similarly to the Ultrascale+ path).
Signed-off-by: Frederik Pfautsch frederik.pfautsch@missinglinkelectronics.com
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mentioned in commit e4b6e6ad
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