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platform/xilinx/vivado: Fix generates of clock signals that originate from phys

Frederik Pfautsch (MLE) requested to merge mle/upstream/fix-clock-signal-assignments into wrpc-v5

Remove default assignments of clock signals when g_use_default_plls = FALSE that actually originate from the phys / transceivers and are thus independant of said generic (signals would have multiple writers / assignements).

Edited by Frederik Pfautsch (MLE)

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