Skip to content
Snippets Groups Projects

platform/xilinx/vivado: Fix generates of clock signals that originate from phys

Merged Frederik Pfautsch (MLE) requested to merge mle/upstream/fix-clock-signal-assignments into wrpc-v5

Remove default assignments of clock signals when g_use_default_plls = FALSE that actually originate from the phys / transceivers and are thus independant of said generic (signals would have multiple writers / assignements).

Edited by Frederik Pfautsch (MLE)

Merge request reports

Loading
Loading

Activity

Filter activity
  • Approvals
  • Assignees & reviewers
  • Comments (from bots)
  • Comments (from users)
  • Commits & branches
  • Edits
  • Labels
  • Lock status
  • Mentions
  • Merge request status
  • Tracking
Please register or sign in to reply