Merge branch 'mle/upstream/fix-clock-signal-assignments' into 'wrpc-v5'

platform/xilinx/vivado: Fix generates of clock signals that originate from phys

See merge request !17

platform/xilinx/xwrc_platform_vivado.vhd

@@ -628,12 +628,8 @@ begin  -- architecture rtl
 
     clk_62m5_sys_o  <= clk_62m5_sys_i;
     clk_62m5_dmtd_o <= clk_62m5_dmtd_i;
-    clk_125m_ref_o  <= clk_125m_ref_i;
-
-    clk_125m_pllref_buf <= clk_125m_ref_i;
 
     pll_locked_o     <= clk_sys_locked_i and clk_dmtd_locked_i;
-    clk_ref_locked_o <= clk_ref_locked_i;
 
     ext_ref_mul_o         <= clk_125m_ext_i;
     ext_ref_mul_locked_o  <= clk_ext_locked_i;