remove unused signals

modules/wr_irig/wr_irig_slave.vhd

@@ -111,8 +111,6 @@ architecture rtl of wr_irig_slave is
   signal sof, synced : std_logic;
   signal marker, irig_data : std_logic;
   signal d_valid, field_valid, smpl_err : std_logic;
-  signal secs : std_logic_vector(7 downto 0);
-  signal mins, hrs, days0, days1, yrs, ctrl0, ctrl1, sbs0, sbs1 : std_logic_vector(8 downto 0);
 
 begin
 

modules/wr_irig/xwr_irig_slave.vhd

@@ -96,7 +96,6 @@ architecture wrapper of xwr_irig_slave is
   signal mins : std_logic_vector(8 downto 0);
   signal hrs  : std_logic_vector(8 downto 0);
   signal days : std_logic_vector(10 downto 0);
-  signal tos  : std_logic_vector(3 downto 0);
   signal yrs  : std_logic_vector(8 downto 0);
   signal ctrl0 : std_logic_vector(8 downto 0);
   signal ctrl1 : std_logic_vector(8 downto 0);