- 09 Feb, 2017 1 commit
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Cesar Prados authored
These changes require also a driver update because the correct AM values have to be written into the ADER registers.
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- 01 Aug, 2016 1 commit
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Cesar Prados authored
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- 28 Jul, 2016 1 commit
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Cesar Prados authored
the submodule is hosted in CERN repo and as long as I could see people without CERN account are having problems to check it out.
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- 27 Jul, 2016 1 commit
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Cesar Prados authored
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- 26 Apr, 2016 2 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- 22 Apr, 2016 1 commit
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Wesley W. Terpstra authored
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- 18 Jul, 2014 2 commits
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Cesar Prados authored
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Cesar Prados authored
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- 03 Apr, 2014 2 commits
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Cesar Prados authored
in comparisons
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Cesar Prados authored
module VME_init
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- 02 Apr, 2014 4 commits
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Cesar Prados authored
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Cesar Prados authored
- compatibility with Wishbone and the VIC interrupt controller - possibility of losing an edge-triggered IRQ and hanging interrupts when different cores trigger interrupts very close to each other. The modified interrupter implements a retry mechanism, that is, if the IRQ line gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle is repeated on the VME bus. signoff Tomas.W.
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Cesar Prados authored
be addressed without conflicts using A24 only disable everything except A24/A32 VME_bus.vhd: reset internal address/AM register when AS is inactive (prevents two cards DTACKing same access bug) --signoff Tomas.W.
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Cesar Prados authored
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- 26 Mar, 2014 1 commit
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Wesley W. Terpstra authored
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- 25 Mar, 2014 1 commit
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Cesar Prados authored
kernel > 3.9, this module it is not compiled.
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- 20 Mar, 2014 4 commits
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Wesley W. Terpstra authored
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Cesar Prados authored
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Cesar Prados authored
The chip tundra doesn't support 8 bit data width transfer, it is emulated from wb master, who provides the select setting for each access. From now on the wb registers can be read/write only through the vme_wb
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Cesar Prados authored
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- 27 Feb, 2014 5 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- 20 Jan, 2014 1 commit
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Cesar Prados authored
generic. Now the the sdb is autogenerated.
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- 15 Jan, 2014 1 commit
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Wesley W. Terpstra authored
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- 14 Jan, 2014 3 commits
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Cesar Prados authored
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Cesar Prados authored
I had it in another repo, but now that the things are working better to start compacting the repos
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Cesar Prados authored
the VME_Wb interface has an additional register for controlling the msi interrupts. The rest of the changes in the VME bus and top file are for backwards compatibility. Now the user can synthesize for legacy interrupts or msi.
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- 16 Dec, 2013 3 commits
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Cesar Prados authored
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Cesar Prados authored
msi_interrupts: add MSI support to VME core. Now the src of an interrupt can be from another module (legacy interrupt) or from the MSI WB bus
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Cesar Prados authored
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- 10 Dec, 2013 1 commit
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Cesar Prados authored
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- 29 Nov, 2013 1 commit
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Wesley W. Terpstra authored
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- 07 Nov, 2013 1 commit
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Wesley W. Terpstra authored
Signed-off-by: Cesar Prados <c.prados@gsi.de>
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- 04 Nov, 2013 1 commit
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Cesar Prados authored
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- 21 Oct, 2013 1 commit
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Cesar Prados authored
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- 04 Oct, 2013 1 commit
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Cesar Prados authored
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