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legacy-vme64x-core
Commit d3b9bd57 authored by Cesar Prados's avatar Cesar Prados
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msi_interrupts: add MSI support to VME core. Now the src of an interrupt can be… 

msi_interrupts: add MSI support to VME core. Now the src of an interrupt can be from another module (legacy interrupt) or from the MSI WB bus
parent 6c8da241
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Showing with 224 additions and 181 deletions
hdl/VME_Buffer.vhd
View file @ d3b9bd57
......@@ -26,8 +26,6 @@ entity VME_Buffer_ctrl is
addr_buff_v2f_o : out std_logic;
addr_buff_f2v_o : out std_logic;
dtack_oe_o : out std_logic;
latch_buff_o : out std_logic
);
end entity;
......@@ -85,8 +83,6 @@ begin
with g_bus_mode select
latch_buff_o <= '1' when LATCHED,
'0' when CLOCKED;
dtack_oe_o <= buffer_stat_i.s_dtack_oe;
-- dir_eo_buff_ctrl : process(clk_i, rst_i)
-- begin
......
hdl/VME_Buffer_pack.vhd
View file @ d3b9bd57
......@@ -38,9 +38,6 @@ package VME_Buffer_pack is
is_d64 : std_logic;
vme_write : std_logic)
return t_VME_BUFFER;
function buffer_irq_function ( fsm : t_IRQMainFSM)
return t_VME_BUFFER;
type bus_mode is ( LATCHED,
CLOCKED);
......@@ -60,8 +57,6 @@ package VME_Buffer_pack is
addr_buff_v2f_o : out std_logic;
addr_buff_f2v_o : out std_logic;
dtack_oe_o : out std_logic;
latch_buff_o : out std_logic
);
end component VME_Buffer_ctrl;
......@@ -96,15 +91,13 @@ package body VME_Buffer_pack is
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '0';
when DECODE_ACCESS =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
vme_buff.s_clk := '0';
when WAIT_FOR_DS | LATCH_DS1 | LATCH_DS2
| LATCH_DS3 | LATCH_DS4 =>
......@@ -124,8 +117,7 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when CHECK_TRANSFER_TYPE | MEMORY_REQ =>
if('1' = is_d64) then
......@@ -143,7 +135,6 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when DATA_TO_BUS | DTACK_LOW | DECIDE_NEXT_CYCLE =>
......@@ -162,7 +153,6 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '1';
when INCREMENT_ADDR | SET_DATA_PHASE =>
......@@ -181,59 +171,18 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when others =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
end case;
return vme_buff;
end buffer_function;
function buffer_irq_function ( fsm : t_IRQMainFSM )
return t_VME_BUFFER is
variable vme_buff : t_VME_BUFFER := c_buffer_default;
begin
case fsm is
when DATA_OUT =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := FPGA2VME;
vme_buff.s_buffer_eo := DATA_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when DTACK =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := FPGA2VME;
vme_buff.s_buffer_eo := DATA_BUFF;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '1';
when others =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
end case;
return vme_buff;
end buffer_irq_function;
end VME_Buffer_pack;
hdl/VME_IRQ_Controller.vhd
View file @ d3b9bd57
......@@ -102,8 +102,6 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.xvme64x_pack.all;
use work.VME_Buffer_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
......@@ -120,11 +118,10 @@ entity VME_IRQ_Controller is
INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (6 downto 0);
VME_DATA_o : out std_logic_vector (31 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
------------------------------------------------------------------
-- VME_DTACK_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector (31 downto 0);
-- VME_DATA_DIR_o : out std_logic);
VME_BUFFER_o : out t_VME_BUFFER);
end VME_IRQ_Controller;
......@@ -135,16 +132,15 @@ architecture Behavioral of VME_IRQ_Controller is
--input signals
signal s_INT_Req_sample : std_logic;
--output signals
--signal s_DTACK_OE_o : std_logic;
signal s_buffer : t_VME_BUFFER;
signal s_DTACK_OE_o : std_logic;
signal s_enable : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0);
signal s_Data : std_logic_vector(31 downto 0);
--
signal s_AS_FallingEdge : std_logic;
signal s_AS_RisingEdge : std_logic;
--type t_IRQMainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal s_currs, s_nexts : t_IRQMainFSM;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal s_currs, s_nexts : t_MainFSM;
signal s_ack_int : std_logic;
signal s_VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal s_VME_DS_latched : std_logic_vector(1 downto 0);
......@@ -197,8 +193,7 @@ begin
DTACKOEOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
--s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
s_buffer <= s_FSM_IRQ.s_buffer;
s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
end if;
end process;
......@@ -353,16 +348,14 @@ begin
when DATA_OUT=>
s_FSM_IRQ <= c_FSM_IRQ;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ.s_buffer <= buffer_irq_function(s_currs);
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when DTACK=>
s_FSM_IRQ <= c_FSM_IRQ;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ.s_buffer <= buffer_irq_function(s_currs);
s_FSM_IRQ.s_DTACK <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when others => null;
end case;
......@@ -427,9 +420,7 @@ begin
s_Data <= x"000000" & INT_Vector_i;
s_enable <= (not s_INT_Req_sample) or ((not s_FSM_IRQ.s_DTACK) and (s_AS_RisingEdge));
-- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
--VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_BUFFER_o <= s_buffer;
VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_IACKOUT_n_o <= s_FSM_IRQ.s_IACKOUT;
end Behavioral;
--===========================================================================
......
hdl/VME_Wb_master_eb.vhd
View file @ d3b9bd57
This diff is collapsed.
hdl/VME_bus.vhd
View file @ d3b9bd57
This diff is collapsed.
hdl/xVME64xCore_Top.vhd
View file @ d3b9bd57
......@@ -40,29 +40,31 @@
entity xVME64xCore_Top is
generic(
-- clock period (ns)
g_clock : integer := c_clk_period; -- 100 MHz
g_clock : integer := c_clk_period; -- 100 MHz
--WB data width:
g_wb_data_width : integer := c_width; -- must be 32 or 64
g_wb_data_width : integer := c_width; -- must be 32 or 64
--WB address width:
g_wb_addr_width : integer := c_addr_width; -- 64 or less
g_wb_addr_width : integer := c_addr_width; -- 64 or less
-- CRAM
g_cram_size : integer := c_CRAM_SIZE;
-- Board ID; each board shall have an unique ID. eg: SVEC_ID = 408.
-- loc: 0x33, 0x37, 0x3B, 0x3F CR space
g_BoardID : integer := c_SVEC_ID; -- 4 bytes: 0x00000198
g_BoardID : integer := c_SVEC_ID; -- 4 bytes: 0x00000198
-- Manufacturer ID: eg the CERN ID is 0x080030
-- loc: 0x27, 0x2B, 0x2F CR space
g_ManufacturerID : integer := c_CERN_ID; -- 3 bytes: 0x080030
g_ManufacturerID : integer := c_CERN_ID; -- 3 bytes: 0x080030
-- Revision ID
-- loc: 0x43, 0x47, 0x4B, 0x4F CR space
g_RevisionID : integer := c_RevisionID; -- 4 bytes: 0x00000001
g_RevisionID : integer := c_RevisionID; -- 4 bytes: 0x00000001
-- Program ID: this is the firmware ID
-- loc: 0x7f CR space
g_ProgramID : integer := 90; -- 1 byte : 0x5a
g_ProgramID : integer := 90; -- 1 byte : 0x5a
-- VME base address setting
g_base_addr : base_addr := GEOGRAPHICAL_ADDR; -- MECHANICALLY or , legacy
g_base_addr : base_addr := GEOGRAPHICAL_ADDR; -- MECHANICALLY or , legacy
-- SDB address
g_sdb_addr : t_wishbone_address := c_sdb_address -- 0x00300000
g_sdb_addr : t_wishbone_address := c_sdb_address; -- 0x00300000;
-- IRQ source
g_irq_src : irq_src := LEGACY -- LEGACY or MSI
);
port(
clk_i : in std_logic;
......@@ -92,7 +94,7 @@
VME_IACKOUT_n_o : out std_logic;
-- VME buffers
--VME_DTACK_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
--VME_DATA_BUFF_o : out t_VME_BUFFER;
--VME_ADDR_BUFF_o : out t_VME_BUFFER;
......@@ -105,9 +107,12 @@
VME_RETRY_OE_o : out std_logic;
-- WishBone
-- WishBone Master to WB Crossbar
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
-- WishBone Slave to MSI WB Crossbar
slave_o : out t_wishbone_slave_out;
slave_i : in t_wishbone_slave_in;
-- IRQ Generator
INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt
......@@ -143,8 +148,8 @@
signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
--signal s_VME_DTACK_OE_VMEbus : std_logic;
--signal s_VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
signal s_VME_DTACK_OE_IRQ : std_logic;
--signal s_VME_DATA_DIR_VMEbus : std_logic;
--signal s_VME_DATA_BUFF_VMEbus : t_VME_BUFFER;
--signal s_VME_DATA_DIR_IRQ : std_logic;
......@@ -176,6 +181,8 @@
signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
signal s_IRQ : std_logic;
signal s_IRQ_i : std_logic;
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
......@@ -258,7 +265,7 @@ begin
IrqrisingEdge : RisEdgeDetection
port map (
sig_i => IRQ_i,
sig_i => s_IRQ_i,
clk_i => clk_i,
RisEdge_o => s_IRQ
);
......@@ -285,23 +292,23 @@ begin
VME_DS_n_i => VME_DS_n_oversampled,
VME_DS_ant_n_i => VME_DS_n_oversampled_1,
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
--VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
VME_ADDR_i => VME_ADDR_i,
VME_ADDR_o => VME_ADDR_o,
VME_BUFFER_o => s_VME_BUFFER_VMEbus,
--VME_ADDR_BUFF_o => VME_ADDR_BUFF_o
VME_BUFFER_o => s_VME_BUFFER_VMEbus,
--VME_ADDR_BUFF_o => VME_ADDR_BUFF_o
--VME_ADDR_DIR_o => VME_ADDR_DIR_o,
--VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_DATA_i => VME_DATA_i,
VME_DATA_o => s_VME_DATA_VMEbus,
--VME_DATA_BUFF_o => s_VME_DATA_BUFF_VMEbus
--VME_DATA_BUFF_o => s_VME_DATA_BUFF_VMEbus
--VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
--VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_i,
VME_IACK_n_i => VME_IACK_n_oversampled,
-- WB
memReq_o => master_o.STB,
memReq_o => master_o.STB,
memAckWB_i => master_i.ACK,
wbData_o => master_o.DAT,
wbData_i => master_i.DAT,
......@@ -312,6 +319,10 @@ begin
err_i => master_i.ERR,
rty_i => master_i.RTY,
stall_i => master_i.STALL,
-- MSI WB slave
slave_o => slave_o;
slave_i => slave_i;
msi_irq_o => s_msi_irq;
-- CR/CSR signals
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
......@@ -357,22 +368,28 @@ begin
s_VME_DATA_IRQ;
VME_DTACK_n_o <= s_VME_DTACK_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DTACK_IRQ;
--VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DTACK_OE_IRQ;
VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DTACK_OE_IRQ;
--VME_DATA_DIR_o <= s_VME_DATA_DIR_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DATA_DIR_IRQ;
--VME_DATA_BUFF_o <= s_VME_DATA_BUFF_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DATA_DIR_IRQ;
VME_BUFFER_o <= s_VME_BUFFER_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_BUFFER_IRQ;
--------------------------------------------------------------------------------
-- Multiplexer for src of IRQ, legacy or MSI
s_IRQ_i <= IRQ_i when g_irq_src = LEGACY else
s_msi_irq; -- MSI
--------------------------------------------------------------------------------
-- Interrupter
Inst_VME_IRQ_Controller: VME_IRQ_Controller port map(
Inst_VME_IRQ_Controller: VME_IRQ_Controller port map(
clk_i => clk_i,
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_AS1_n_i => VME_AS_n_i,
VME_AS1_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
......@@ -382,9 +399,10 @@ begin
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => s_VME_DTACK_IRQ,
VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
VME_DATA_o => s_VME_DATA_IRQ,
--VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
--VME_DATA_DIR_o => s_VME_DATA_DIR_IRQ
--VME_DATA_BUFF_o => s_VME_DATA_BUFF_IRQ
VME_BUFFER_o => s_VME_BUFFER_IRQ
);
......
hdl/xvme64x_pack.vhd
View file @ d3b9bd57
......@@ -49,16 +49,15 @@ package xvme64x_pack is
s_clk : std_logic;
s_buffer_eo : vme_buffer_eo;
s_latch_oe : std_logic;
s_dtack_oe : std_logic;
end record;
type t_FSM is
record
s_memReq : std_logic;
s_decode : std_logic;
s_dtackOE : std_logic;
s_mainDTACK : std_logic;
s_buffer : t_VME_BUFFER;
--s_dtackOE : std_logic;
--s_dataBuf : t_VME_BUFFER;
--s_addrBuf : t_VME_BUFFER;
--s_dataDir : std_logic;
......@@ -81,12 +80,12 @@ package xvme64x_pack is
record
s_IACKOUT : std_logic;
--s_DataDir : std_logic;
--s_DTACK_OE : std_logic;
s_buffer : t_VME_BUFFER;
s_DTACK : std_logic;
s_enableIRQ : std_logic;
s_resetIRQ : std_logic;
s_DSlatch : std_logic;
s_DTACK_OE : std_logic;
end record;
--_______________________________________________________________________________
......@@ -238,7 +237,6 @@ package xvme64x_pack is
s_dataDir => '0',
s_clk => '0',
s_buffer_eo => ADDR_BUFF,
s_dtack_oe => '0',
s_latch_oe => '0'
);
-- Main Finite State machine signals default:
......@@ -250,9 +248,9 @@ package xvme64x_pack is
constant c_FSM_default : t_FSM :=(
s_memReq => '0',
s_decode => '0',
s_dtackOE => '0',
s_mainDTACK => '1',
s_buffer => c_buffer_default,
--s_dtackOE => '0',
--s_dataDir => '0',
--s_dataOE => '0',
--s_addrDir => '0', -- during IACK cycle the ADDR lines are input
......@@ -272,12 +270,12 @@ package xvme64x_pack is
constant c_FSM_IRQ : t_FSM_IRQ :=(
s_IACKOUT => '1',
--s_DataDir => '0',
--s_DTACK_OE => '0',
s_buffer => c_buffer_default,
s_DTACK => '1',
s_enableIRQ => '0',
s_resetIRQ => '1',
s_DSlatch => '0'
s_DSlatch => '0',
s_DTACK_OE => '0'
);
-- CSR address:
......@@ -422,17 +420,17 @@ package xvme64x_pack is
-- TWOe_END_2
);
type t_IRQMainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS,
CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
type t_initState is ( IDLE,
SET_ADDR,
GET_DATA,
END_INIT
type t_initState is ( IDLE,
SET_ADDR,
GET_DATA,
END_INIT
);
type base_addr is ( GEOGRAPHICAL_ADDR,
MECHANICALLY
);
type irq_src is ( LEGACY,
MSI
);
type t_FUNC_32b_array is array (0 to 7) of unsigned(31 downto 0); -- ADER register array
type t_FUNC_64b_array is array (0 to 7) of unsigned(63 downto 0); -- AMCAP register array
......@@ -463,10 +461,11 @@ function f_latchDS (clk_period : integer) return integer;
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96; -- 0x00000060
g_base_addr : base_addr := MECHANICALLY;
g_sdb_addr : t_wishbone_address := c_sdb_address
g_sdb_addr : t_wishbone_address := c_sdb_address;
g_irq_src : irq_src := LEGACY
);
port(
-- VME signals:
-- VME signals:
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
......@@ -489,12 +488,15 @@ function f_latchDS (clk_period : integer) return integer;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_Buffer_o : out t_VME_BUFFER;
MASTER_O : out t_wishbone_master_out;
MASTER_I : in t_wishbone_master_in;
SLAVE_O : out t_wishbone_slave_out;
SLAVE_I : in t_wishbone_slave_in;
-- IRQ Generator
IRQ_i : in std_logic;
INT_ack_o : out std_logic;
......@@ -530,6 +532,9 @@ function f_latchDS (clk_period : integer) return integer;
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
slave_o : out t_wishbone_slave_out;
slave_i : in t_wishbone_slave_in;
msi_irq_o : out std_logic;
CRAMdata_i : in std_logic_vector(7 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
CSRData_i : in std_logic_vector(7 downto 0);
......@@ -551,7 +556,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_DTACK_n_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_BUFFER_o : out t_VME_BUFFER;
......@@ -668,7 +673,8 @@ function f_latchDS (clk_period : integer) return integer;
g_ManufacturerID : integer := c_CERN_ID;
g_RevisionID : integer := c_RevisionID;
g_ProgramID : integer := 96;
g_base_addr : base_addr:= GEOGRAPHICAL_ADDR
g_base_addr : base_addr:= GEOGRAPHICAL_ADDR;
g_irq_addr : integer := LEGACY
);
port(
......@@ -743,7 +749,7 @@ function f_latchDS (clk_period : integer) return integer;
);
end component VME_Am_Match;
component VME_Wb_master is
component VME_Wb_Interface is
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
......@@ -773,10 +779,13 @@ function f_latchDS (clk_period : integer) return integer;
WBdata_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
WbSel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
funct_sel : in std_logic_vector (7 downto 0);
RW_o : out std_logic
funct_sel : in std_logic_vector (7 downto 0);
RW_o : out std_logic;
slave_o : out t_wishbone_slave_out;
slave_i : in t_wishbone_slave_in;
msi_irq_o : out std_logic
);
end component VME_Wb_master;
end component VME_Wb_Interface;
component VME_Init is
port(
......@@ -920,7 +929,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
--VME_DATA_DIR_o : out std_logic
VME_BUFFER_o : out t_VME_BUFFER
......
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