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Cesar Prados authored
- compatibility with Wishbone and the VIC interrupt controller - possibility of losing an edge-triggered IRQ and hanging interrupts when different cores trigger interrupts very close to each other. The modified interrupter implements a retry mechanism, that is, if the IRQ line gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle is repeated on the VME bus. signoff Tomas.W.
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