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legacy-vme64x-core
Commit 20906542 authored by Cesar Prados's avatar Cesar Prados
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msi_interrupts: fix error merging: pull --rebase

parent d3b9bd57
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Showing with 113 additions and 44 deletions
hdl/VME_Buffer.vhd
View file @ 20906542
......@@ -26,6 +26,8 @@ entity VME_Buffer_ctrl is
addr_buff_v2f_o : out std_logic;
addr_buff_f2v_o : out std_logic;
dtack_oe_o : out std_logic;
latch_buff_o : out std_logic
);
end entity;
......@@ -83,6 +85,8 @@ begin
with g_bus_mode select
latch_buff_o <= '1' when LATCHED,
'0' when CLOCKED;
dtack_oe_o <= buffer_stat_i.s_dtack_oe;
-- dir_eo_buff_ctrl : process(clk_i, rst_i)
-- begin
......
hdl/VME_Buffer_pack.vhd
View file @ 20906542
......@@ -38,6 +38,9 @@ package VME_Buffer_pack is
is_d64 : std_logic;
vme_write : std_logic)
return t_VME_BUFFER;
function buffer_irq_function ( fsm : t_IRQMainFSM)
return t_VME_BUFFER;
type bus_mode is ( LATCHED,
CLOCKED);
......@@ -57,6 +60,8 @@ package VME_Buffer_pack is
addr_buff_v2f_o : out std_logic;
addr_buff_f2v_o : out std_logic;
dtack_oe_o : out std_logic;
latch_buff_o : out std_logic
);
end component VME_Buffer_ctrl;
......@@ -91,13 +96,15 @@ package body VME_Buffer_pack is
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '0';
when DECODE_ACCESS =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
when WAIT_FOR_DS | LATCH_DS1 | LATCH_DS2
| LATCH_DS3 | LATCH_DS4 =>
......@@ -117,7 +124,8 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when CHECK_TRANSFER_TYPE | MEMORY_REQ =>
if('1' = is_d64) then
......@@ -135,6 +143,7 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when DATA_TO_BUS | DTACK_LOW | DECIDE_NEXT_CYCLE =>
......@@ -153,6 +162,7 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '1';
when INCREMENT_ADDR | SET_DATA_PHASE =>
......@@ -171,18 +181,59 @@ package body VME_Buffer_pack is
end if;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when others =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
end case;
return vme_buff;
end buffer_function;
end VME_Buffer_pack;
function buffer_irq_function ( fsm : t_IRQMainFSM )
return t_VME_BUFFER is
variable vme_buff : t_VME_BUFFER := c_buffer_default;
begin
case fsm is
when DATA_OUT =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := FPGA2VME;
vme_buff.s_buffer_eo := DATA_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '1';
when DTACK =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := FPGA2VME;
vme_buff.s_buffer_eo := DATA_BUFF;
vme_buff.s_clk := '1';
vme_buff.s_dtack_oe := '1';
when others =>
vme_buff.s_addrDir := VME2FPGA;
vme_buff.s_dataDir := VME2FPGA;
vme_buff.s_buffer_eo := ADDR_BUFF;
vme_buff.s_clk := '0';
vme_buff.s_dtack_oe := '0';
end case;
return vme_buff;
end buffer_irq_function;
end VME_Buffer_pack;
hdl/VME_IRQ_Controller.vhd
View file @ 20906542
......@@ -102,6 +102,8 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.xvme64x_pack.all;
use work.VME_Buffer_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
......@@ -118,10 +120,11 @@ entity VME_IRQ_Controller is
INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (6 downto 0);
VME_DATA_o : out std_logic_vector (31 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector (31 downto 0);
------------------------------------------------------------------
-- VME_DTACK_OE_o : out std_logic;
-- VME_DATA_DIR_o : out std_logic);
VME_BUFFER_o : out t_VME_BUFFER);
end VME_IRQ_Controller;
......@@ -132,15 +135,16 @@ architecture Behavioral of VME_IRQ_Controller is
--input signals
signal s_INT_Req_sample : std_logic;
--output signals
signal s_DTACK_OE_o : std_logic;
--signal s_DTACK_OE_o : std_logic;
signal s_buffer : t_VME_BUFFER;
signal s_enable : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0);
signal s_Data : std_logic_vector(31 downto 0);
--
signal s_AS_FallingEdge : std_logic;
signal s_AS_RisingEdge : std_logic;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal s_currs, s_nexts : t_MainFSM;
--type t_IRQMainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal s_currs, s_nexts : t_IRQMainFSM;
signal s_ack_int : std_logic;
signal s_VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal s_VME_DS_latched : std_logic_vector(1 downto 0);
......@@ -193,7 +197,8 @@ begin
DTACKOEOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
--s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
s_buffer <= s_FSM_IRQ.s_buffer;
end if;
end process;
......@@ -348,14 +353,16 @@ begin
when DATA_OUT=>
s_FSM_IRQ <= c_FSM_IRQ;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ.s_buffer <= buffer_irq_function(s_currs);
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when DTACK=>
s_FSM_IRQ <= c_FSM_IRQ;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ.s_buffer <= buffer_irq_function(s_currs);
s_FSM_IRQ.s_DTACK <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when others => null;
end case;
......@@ -420,7 +427,9 @@ begin
s_Data <= x"000000" & INT_Vector_i;
s_enable <= (not s_INT_Req_sample) or ((not s_FSM_IRQ.s_DTACK) and (s_AS_RisingEdge));
-- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
VME_DTACK_OE_o <= s_DTACK_OE_o;
--VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_BUFFER_o <= s_buffer;
VME_IACKOUT_n_o <= s_FSM_IRQ.s_IACKOUT;
end Behavioral;
--===========================================================================
......
hdl/VME_bus.vhd
View file @ 20906542
......@@ -99,7 +99,7 @@ entity VME_bus is
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_DS_ant_n_i : in std_logic_vector(1 downto 0);
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
......@@ -176,7 +176,7 @@ architecture RTL of VME_bus is
signal s_LWORDinput : std_logic;
-- External buffer signals
signal s_dtackOE : std_logic;
--signal s_dtackOE : std_logic;
signal s_buffer : t_VME_BUFFER;
--signal s_dataBuf : t_VME_BUFFER;
--signal s_dataDir : std_logic;
......@@ -351,7 +351,7 @@ begin
--VME_ADDR_BUFF_o <= s_addrBuf;
VME_BUFFER_o <= s_buffer;
VME_DTACK_OE_o <= s_dtackOE;
--VME_DTACK_OE_o <= s_dtackOE;
-- VME DTACK:
VME_DTACK_n_o <= s_mainDTACK;
......@@ -486,7 +486,7 @@ with s_addressingType select
-------------------------------------MAIN FSM--------------------------------|
s_memReq <= s_FSM.s_memReq;
s_decode <= s_FSM.s_decode;
s_dtackOE <= s_FSM.s_dtackOE;
--s_dtackOE <= s_FSM.s_dtackOE;
s_mainDTACK <= s_FSM.s_mainDTACK;
--s_dataBuf <= s_FMS.s_dataBuf;
--s_addrBuf <= s_FMS.s_addrBuf;
......@@ -555,7 +555,7 @@ with s_addressingType select
when WAIT_FOR_DS => -- wait until DS /= "11"
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
s_FSM.s_DSlatch <= '1';
......@@ -572,7 +572,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -590,7 +590,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -608,7 +608,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -626,7 +626,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -640,7 +640,7 @@ with s_addressingType select
when CHECK_TRANSFER_TYPE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
......@@ -662,7 +662,7 @@ with s_addressingType select
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_memReq signal
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -684,7 +684,7 @@ with s_addressingType select
when DATA_TO_BUS =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -697,7 +697,7 @@ with s_addressingType select
when DTACK_LOW =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -725,7 +725,7 @@ with s_addressingType select
when DECIDE_NEXT_CYCLE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -745,7 +745,7 @@ with s_addressingType select
when INCREMENT_ADDR =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
......@@ -756,7 +756,7 @@ with s_addressingType select
when SET_DATA_PHASE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_buffer <= buffer_function(s_mainFSMstate, s_is_d64, VME_WRITE_n_i);
s_FSM.s_dataPhase <= '1';
......
hdl/xVME64xCore_Top.vhd
View file @ 20906542
......@@ -94,7 +94,7 @@
VME_IACKOUT_n_o : out std_logic;
-- VME buffers
VME_DTACK_OE_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
--VME_DATA_BUFF_o : out t_VME_BUFFER;
--VME_ADDR_BUFF_o : out t_VME_BUFFER;
......@@ -148,8 +148,8 @@
signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
signal s_VME_DTACK_OE_IRQ : std_logic;
--signal s_VME_DTACK_OE_VMEbus : std_logic;
--signal s_VME_DTACK_OE_IRQ : std_logic;
--signal s_VME_DATA_DIR_VMEbus : std_logic;
--signal s_VME_DATA_BUFF_VMEbus : t_VME_BUFFER;
--signal s_VME_DATA_DIR_IRQ : std_logic;
......@@ -292,7 +292,7 @@ begin
VME_DS_n_i => VME_DS_n_oversampled,
VME_DS_ant_n_i => VME_DS_n_oversampled_1,
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
--VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
VME_ADDR_i => VME_ADDR_i,
VME_ADDR_o => VME_ADDR_o,
......@@ -368,8 +368,8 @@ begin
s_VME_DATA_IRQ;
VME_DTACK_n_o <= s_VME_DTACK_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DTACK_IRQ;
VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DTACK_OE_IRQ;
--VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DTACK_OE_IRQ;
--VME_DATA_DIR_o <= s_VME_DATA_DIR_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DATA_DIR_IRQ;
--VME_DATA_BUFF_o <= s_VME_DATA_BUFF_VMEbus when VME_IACK_n_oversampled ='1' else
......@@ -399,7 +399,7 @@ begin
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => s_VME_DTACK_IRQ,
VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
--VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
VME_DATA_o => s_VME_DATA_IRQ,
--VME_DATA_DIR_o => s_VME_DATA_DIR_IRQ
--VME_DATA_BUFF_o => s_VME_DATA_BUFF_IRQ
......
hdl/xvme64x_pack.vhd
View file @ 20906542
......@@ -49,13 +49,14 @@ package xvme64x_pack is
s_clk : std_logic;
s_buffer_eo : vme_buffer_eo;
s_latch_oe : std_logic;
s_dtack_oe : std_logic;
end record;
type t_FSM is
record
s_memReq : std_logic;
s_decode : std_logic;
s_dtackOE : std_logic;
--s_dtackOE : std_logic;
s_mainDTACK : std_logic;
s_buffer : t_VME_BUFFER;
--s_dataBuf : t_VME_BUFFER;
......@@ -85,7 +86,7 @@ package xvme64x_pack is
s_enableIRQ : std_logic;
s_resetIRQ : std_logic;
s_DSlatch : std_logic;
s_DTACK_OE : std_logic;
--s_DTACK_OE : std_logic;
end record;
--_______________________________________________________________________________
......@@ -237,6 +238,7 @@ package xvme64x_pack is
s_dataDir => '0',
s_clk => '0',
s_buffer_eo => ADDR_BUFF,
s_dtack_oe => '0',
s_latch_oe => '0'
);
-- Main Finite State machine signals default:
......@@ -248,7 +250,7 @@ package xvme64x_pack is
constant c_FSM_default : t_FSM :=(
s_memReq => '0',
s_decode => '0',
s_dtackOE => '0',
--s_dtackOE => '0',
s_mainDTACK => '1',
s_buffer => c_buffer_default,
--s_dataDir => '0',
......@@ -270,12 +272,12 @@ package xvme64x_pack is
constant c_FSM_IRQ : t_FSM_IRQ :=(
s_IACKOUT => '1',
--s_DataDir => '0',
--s_DTACK_OE => '0'
s_buffer => c_buffer_default,
s_DTACK => '1',
s_enableIRQ => '0',
s_resetIRQ => '1',
s_DSlatch => '0',
s_DTACK_OE => '0'
);
-- CSR address:
......@@ -420,6 +422,9 @@ package xvme64x_pack is
-- TWOe_END_2
);
type t_IRQMainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS,
CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
type t_initState is ( IDLE,
SET_ADDR,
GET_DATA,
......@@ -488,7 +493,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_Buffer_o : out t_VME_BUFFER;
......@@ -556,7 +561,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_BUFFER_o : out t_VME_BUFFER;
......@@ -929,7 +934,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
--VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
--VME_DATA_DIR_o : out std_logic
VME_BUFFER_o : out t_VME_BUFFER
......
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