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legacy-vme64x-core
Commit c141c98f authored by Cesar Prados's avatar Cesar Prados
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vme-core: update the core for the new wb slave interface

parent dffea583
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Showing with 51 additions and 12 deletions
hdl/VME_Wb_master_eb.vhd
View file @ c141c98f
......@@ -40,7 +40,7 @@ use work.wishbone_pkg.all;
--===========================================================================
entity VME_Wb_Interface is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_wb_addr_width : integer := c_addr_width;
g_family : string := "Arria II VME-WB";
g_sdb_addr : t_wishbone_address := c_sdb_address);
......
hdl/xVME64xCore_Top.vhd
View file @ c141c98f
......@@ -84,11 +84,11 @@
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_o : out std_logic_vector(6 downto 0); -- the same as []*
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
......@@ -114,6 +114,9 @@
-- WishBone Slave to MSI WB Crossbar
slave_o : out t_wishbone_slave_out;
slave_i : in t_wishbone_slave_in;
-- Wishbone Slave for VME info
info_slave_o : out t_wishbone_slave_out;
info_slave_i : in t_wishbone_slave_in;
-- IRQ Generator
INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt
......@@ -216,13 +219,13 @@ begin
);
-- DSinputSample : RegInputSample
RegInputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_reg_1 <= VME_DS_n_i;
s_reg_2 <= s_reg_1;
VME_DS_n_oversampled <= s_reg_2;
end if;
RegInputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_reg_1 <= VME_DS_n_i;
s_reg_2 <= s_reg_1;
VME_DS_n_oversampled <= s_reg_2;
end if;
end process;
-- to avoid timing problem during BLT and MBLT accesses
......@@ -457,6 +460,15 @@ begin
INT_Vector => s_INT_Vector
);
vme_info : VME_Wb_slave
port map(
clk_i => clk_i,
rstn_i => rst_n_i,
wb_slave_i => info_slave_i,
wb_slave_o => info_slave_o,
ga_i => VME_GA_oversampled);
end RTL;
--===========================================================================
-- Architecture end
......
hdl/xvme64x_pack.vhd
View file @ c141c98f
......@@ -106,7 +106,23 @@ package xvme64x_pack is
version => x"00000001",
date => x"20120308",
name => "IRQ_VME ")));
constant c_vme_info_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000ffff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"22FFEE84",
version => x"00000001",
date => x"20140701",
name => "INFO_VME ")));
--SDB address
constant c_sdb_address : t_wishbone_address := x"00300000";
--WB data width:
......@@ -521,6 +537,8 @@ function f_latchDS (clk_period : integer) return integer;
MASTER_I : in t_wishbone_master_in;
SLAVE_O : out t_wishbone_slave_out;
SLAVE_I : in t_wishbone_slave_in;
INFO_SLAVE_O : out t_wishbone_slave_out;
INFO_SLAVE_I : in t_wishbone_slave_in;
-- IRQ Generator
IRQ_i : in std_logic;
......@@ -976,6 +994,15 @@ function f_latchDS (clk_period : integer) return integer;
);
end component VME_CRAM;
component VME_Wb_slave is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
wb_slave_i : in t_wishbone_slave_in;
wb_slave_o : out t_wishbone_slave_out;
ga_i : std_logic_vector(5 downto 0));
end component VME_Wb_slave;
end xvme64x_pack;
package body xvme64x_pack is
......
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