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legacy-vme64x-core
Commit 63d7dc7c authored by Cesar Prados's avatar Cesar Prados
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vme_core: using top reset core for reseting the 

          module VME_init
parent cc99c478
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Showing with 32 additions and 22 deletions
hdl/VME_Init.vhd
View file @ 63d7dc7c
......@@ -38,7 +38,8 @@ use work.xvme64x_pack.all;
--===========================================================================
entity VME_Init is
Port ( clk_i : in std_logic;
RSTedge_i : in std_logic;
--RSTedge_i : in std_logic;
rst_n_i : in std_logic;
CRAddr_i : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount_o : out std_logic_vector (8 downto 0);
......@@ -109,7 +110,8 @@ begin
p_coreInit : process(clk_i)
begin
if rising_edge(clk_i) then
if RSTedge_i = '1' then
--if RSTedge_i = '1' then
if rst_n_i = '0' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
......
hdl/VME_bus.vhd
View file @ 63d7dc7c
......@@ -87,6 +87,7 @@ entity VME_bus is
);
port(
clk_i : in std_logic; -- 125 Mhz
rst_n_i : in std_logic;
reset_o : out std_logic; -- to the Interrupt Generator and IRQ controller
-- VME signals
VME_RST_n_i : in std_logic;
......@@ -209,7 +210,7 @@ architecture RTL of VME_bus is
signal s_DSlatched : std_logic_vector(1 downto 0); -- Stores DS
signal s_AMlatched : std_logic_vector(5 downto 0); --Latch on AS f. edge
signal s_XAM : unsigned(7 downto 0); -- Stores received XAM
signal s_RSTedge : std_logic;
--signal s_RSTedge : std_logic;
-- Type of data transfer (depending on VME_DS_n, VME_LWORD_n and VME_ADDR(1))
signal s_typeOfDataTransfer : t_typeOfDataTransfer;
......@@ -328,7 +329,8 @@ begin
s_is_d64 <= '1' when s_sel= "11111111" else '0'; --used to drive the VME_ADDR_DIR_o
---------
s_RW <= VME_WRITE_n_i;
s_reset <= not(VME_RST_n_i) or s_sw_reset; -- hw and sw reset
--s_reset <= not(VME_RST_n_i) or s_sw_reset; -- hw and sw reset
s_reset <= (not rst_n_i) or not(VME_RST_n_i) or s_sw_reset; -- hw and sw reset
reset_o <= s_reset; -- Asserted when high
-------------------------------------------------------------------------
......@@ -460,12 +462,12 @@ begin
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
s_addrWidth <= s_addrWidth1;
end if;
end process;
--process(clk_i)
--begin
--if rising_edge(clk_i) then
s_addrWidth <= s_addrWidth1;
--end if;
--end process;
-- To implement the A32 2eVME and A32 2eSST accesses the following logic
-- must be changed:
......@@ -1406,7 +1408,8 @@ with s_addressingType select
s_initReadCounter <= unsigned(s_initReadCounter1);
Inst_VME_Init: VME_Init port map(
clk_i => clk_i,
RSTedge_i => s_RSTedge,
--RSTedge_i => s_RSTedge,
rst_n_i => rst_n_i,
CRAddr_i => std_logic_vector(s_CRaddr),
CRdata_i => CRdata_i,
InitReadCount_o => s_initReadCounter1,
......@@ -1452,12 +1455,12 @@ with s_addressingType select
FallEdge_o => s_VMEaddrLatch
);
RSTrisingEdge : RisEdgeDetection
port map (
sig_i => s_reset,
clk_i => clk_i,
RisEdge_o => s_RSTedge
);
-- RSTrisingEdge : RisEdgeDetection
-- port map (
-- sig_i => s_reset,
-- clk_i => clk_i,
-- RisEdge_o => s_RSTedge
-- );
ASrisingEdge : RisEdgeDetection
port map (
......
hdl/xVME64xCore_Top.vhd
View file @ 63d7dc7c
......@@ -67,9 +67,10 @@
g_irq_src : irq_src := LEGACY -- LEGACY or MSI
);
port(
clk_i : in std_logic;
clk_i : in std_logic;
-- for the IRQ_Generator and relative registers
reset_o : out std_logic; -- asserted when '1'
--reset_o : out std_logic; -- asserted when '1'
rst_n_i : in std_logic; -- asserted when '1'
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; -- asserted when '0'
......@@ -280,6 +281,7 @@ begin
port map(
clk_i => clk_i,
reset_o => s_reset, -- asserted when '1'
rst_n_i => rst_n_i,
-- VME
VME_RST_n_i => VME_RST_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
......@@ -359,7 +361,7 @@ begin
VME_IRQ_o <= s_VME_IRQ_n_o; -- My buffers doesn't invert the logic!!!!!
--WE_o <= not s_RW;
master_o.we <= not s_RW;
reset_o <= s_reset;
--reset_o <= s_reset;
INT_ack_o <= s_VME_DTACK_IRQ;
--------------------------------------------------------------------------------
--Multiplexer added on the output signal used by either VMEbus.vhd and the IRQ_controller.vhd
......
hdl/xvme64x_pack.vhd
View file @ 63d7dc7c
......@@ -491,6 +491,7 @@ function f_latchDS (clk_period : integer) return integer;
port(
-- VME signals:
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
......@@ -524,7 +525,7 @@ function f_latchDS (clk_period : integer) return integer;
-- IRQ Generator
IRQ_i : in std_logic;
INT_ack_o : out std_logic;
reset_o : out std_logic;
--reset_o : out std_logic;
-- for debug:
debug : out std_logic_vector(7 downto 0)
......@@ -541,6 +542,7 @@ function f_latchDS (clk_period : integer) return integer;
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
......@@ -814,9 +816,10 @@ function f_latchDS (clk_period : integer) return integer;
component VME_Init is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
CRAddr_i : in std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
RSTedge_i : in std_logic;
--RSTedge_i : in std_logic;
InitReadCount_o : out std_logic_vector(8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector(23 downto 0);
......
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