irq_controller: irq line level-sensitive. There are two reasons for doing so:

- compatibility with Wishbone and the VIC interrupt controller - possibility of losing an edge-triggered IRQ and hanging interrupts when different cores trigger interrupts very close to each other. The modified interrupter implements a retry mechanism, that is, if the IRQ line gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle is repeated on the VME bus. signoff Tomas.W.

irq_controller: irq line level-sensitive. There are two reasons for doing so:
- compatibility with Wishbone and the VIC interrupt controller - possibility of losing an edge-triggered IRQ and hanging interrupts when different cores trigger interrupts very close to each other. The modified interrupter implements a retry mechanism, that is, if the IRQ line gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle is repeated on the VME bus. signoff Tomas.W.
b8a471f1 · Cesar Prados · 785cd574 · b8a471f1 · b8a471f1 · b8a471f1
Commit b8a471f1 authored Apr 02, 2014 by Cesar Prados
Showing with 203 additions and 311 deletions

VME_Buffer_pack.vhd hdl/VME_Buffer_pack.vhd +4 -4

VME_IRQ_Controller.vhd hdl/VME_IRQ_Controller.vhd +184 -295

xVME64xCore_Top.vhd hdl/xVME64xCore_Top.vhd +10 -10

xvme64x_pack.vhd hdl/xvme64x_pack.vhd +5 -2

No files found.
--- a/hdl/VME_Buffer_pack.vhd
+++ b/hdl/VME_Buffer_pack.vhd
@@ -39,7 +39,7 @@ package VME_Buffer_pack is
                              vme_write    : std_logic)
                            return t_VME_BUFFER;

-   function buffer_irq_function ( fsm      : t_IRQMainFSM)
+   function buffer_irq_function ( fsm      : t_irq_main_state)
                            return t_VME_BUFFER; 
                            
   type bus_mode is (  LATCHED,
@@ -196,7 +196,7 @@ package body VME_Buffer_pack is
   end buffer_function;


-   function buffer_irq_function ( fsm  : t_IRQMainFSM )
+   function buffer_irq_function ( fsm  : t_irq_main_state )
                            return t_VME_BUFFER is

        variable vme_buff       : t_VME_BUFFER  := c_buffer_default;
@@ -205,7 +205,7 @@ package body VME_Buffer_pack is

        case fsm is         
        
-           when DATA_OUT => 
+           when CHECK  => 

               vme_buff.s_addrDir	:= VME2FPGA;
 					vme_buff.s_dataDir 	:= FPGA2VME;
@@ -227,7 +227,7 @@ package body VME_Buffer_pack is
 					vme_buff.s_dataDir 	:= VME2FPGA;
               vme_buff.s_buffer_eo := ADDR_BUFF;
 					vme_buff.s_clk       := '0'; 
-               vme_buff.s_dtack_oe  := '0';
+               vme_buff.s_dtack_oe  := '1';

 			end case;


--- a/hdl/VME_IRQ_Controller.vhd
+++ b/hdl/VME_IRQ_Controller.vhd
--- a/hdl/xVME64xCore_Top.vhd
+++ b/hdl/xVME64xCore_Top.vhd
@@ -180,7 +180,6 @@
  signal s_BAR                     : std_logic_vector(4 downto 0);
  signal s_time                    : std_logic_vector(39 downto 0);
  signal s_bytes                   : std_logic_vector(12 downto 0);
-  signal s_IRQ                     : std_logic;
  signal s_IRQ_i                   : std_logic;
  signal s_msi_irq                 : std_logic;
  
@@ -263,12 +262,12 @@ begin
              clk_i => clk_i
            );			
 				
-  IrqrisingEdge : RisEdgeDetection
-  port map (
-              sig_i      => s_IRQ_i,
-              clk_i      => clk_i,
-              RisEdge_o  => s_IRQ
-          );
+--  IrqrisingEdge : RisEdgeDetection
+--  port map (
+--              sig_i      => s_IRQ_i,
+--              clk_i      => clk_i,
+--              RisEdge_o  => s_IRQ
+--          );
 				
  Inst_VME_bus: VME_bus 
  generic map(
@@ -389,13 +388,14 @@ begin
 	         	 reset_n_i         => s_reset_IRQ,  -- asserted when low
 		          VME_IACKIN_n_i    => VME_IACKIN_n_oversampled,
         		 VME_AS_n_i        => VME_AS_n_oversampled,
-                VME_AS1_n_i       => VME_AS_n_i,
+                --VME_AS1_n_i       => VME_AS_n_i,
 	          	 VME_DS_n_i        => VME_DS_n_oversampled,
-        		    VME_LWORD_n_i     => VME_LWORD_n_i,
+        		    --VME_LWORD_n_i     => VME_LWORD_n_i,
         		 VME_ADDR_123_i    => VME_ADDR_i(3 downto 1),
         		 INT_Level_i       => s_INT_Level,
         		 INT_Vector_i      => s_INT_Vector ,
-	          	 INT_Req_i         => s_IRQ,
+	          	 --INT_Req_i         => s_IRQ,
+	          	 INT_Req_i         => s_IRQ_i,
 		          VME_IRQ_n_o       => s_VME_IRQ_n_o,
         		 VME_IACKOUT_n_o   => VME_IACKOUT_n_o,
         		 VME_DTACK_n_o     => s_VME_DTACK_IRQ,

--- a/hdl/xvme64x_pack.vhd
+++ b/hdl/xvme64x_pack.vhd
@@ -441,6 +441,9 @@ package xvme64x_pack is
   type t_IRQMainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, 
                         CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);

+  type t_irq_main_state is (IDLE, IRQ, WAIT_AS, WAIT_DS, CHECK, DATA_OUT, 
+                        DTACK, IACKOUT1, IACKOUT2, SCHEDULE_IRQ);
+
   type t_initState is (         IDLE,            
                                 SET_ADDR,
                                 GET_DATA,
@@ -940,9 +943,9 @@ function f_latchDS (clk_period : integer) return integer;
                        reset_n_i       : in  std_logic;
                        VME_IACKIN_n_i  : in  std_logic;
                        VME_AS_n_i      : in  std_logic;
-								VME_AS1_n_i     : in  std_logic;
+								--VME_AS1_n_i     : in  std_logic;
                        VME_DS_n_i      : in  std_logic_vector(1 downto 0);
-                        VME_LWORD_n_i   : in  std_logic;
+                        --VME_LWORD_n_i   : in  std_logic;
                        VME_ADDR_123_i  : in  std_logic_vector(2 downto 0);
                        INT_Level_i     : in  std_logic_vector(7 downto 0);
                        INT_Vector_i    : in  std_logic_vector(7 downto 0);