in comparisons

          module VME_init

    - compatibility with Wishbone and the VIC interrupt controller
    - possibility of losing an edge-triggered IRQ and hanging interrupts when
      different cores trigger interrupts very close to each other.
    The modified interrupter implements a retry mechanism, that is, if the IRQ line
    gets stuck for longer than certain period (g_retry_timeout), an IRQ cycle
    is repeated on the VME bus.

signoff Tomas.W.

             be addressed without conflicts using A24 only
             disable everything except A24/A32
VME_bus.vhd: reset internal address/AM register when AS is inactive (prevents
             two cards DTACKing same access bug)

--signoff Tomas.W.

          kernel > 3.9, this module it is not compiled.

The chip tundra doesn't support 8 bit data width transfer, it is emulated from wb master, who
provides the select setting for each access. From now on the wb registers can be read/write
only through the vme_wb

generic. Now the the sdb is autogenerated.

I had it in another repo, but now that the things are working better to start compacting the repos

   the VME_Wb interface has an additional register for controlling
   the msi interrupts. The rest of the changes in the VME bus and top
   file are for backwards compatibility. Now the user can synthesize
   for legacy interrupts or msi.

msi_interrupts: add MSI support to VME core. Now the src of an interrupt can be from another module (legacy interrupt) or from the MSI WB bus

Signed-off-by: Cesar Prados <c.prados@gsi.de>

       in the first commit is missing:
        doc folder
        cards example
        wishbone MSI interrupt