- 03 Apr, 2023 1 commit
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Nathan Pittet authored
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- 15 Mar, 2023 1 commit
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Nathan Pittet authored
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- 17 Feb, 2023 1 commit
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Nathan Pittet authored
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- 15 Dec, 2022 28 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Nathan Pittet authored
dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.
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Nathan Pittet authored
dsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.
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Nathan Pittet authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
Note: mostly untested code. Licensing to be fixed.
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
- Rework simdrv_defs into a package - Use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use) - Added AXI4 BFMs from the PULP project library - Added a bunch of simulation drivers (for the VUART & LM32 MCS cores) - Added a trivial unit test/logging "framework" (logger.svh) Note these changes will break your legacy testbenches, here's how to fix the most common issues: - Replace the includes of simdrv_defs.svh indo an include of "gencores_sim_defs.svh" followed by import of gencores_sim_pkg package - If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues instead of dynamic arrays
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- 10 Oct, 2022 1 commit
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Pascal Bos authored
Issue occurred when "wb.ack" became active in the same cycle as "wb.stall" became inactive. The "RESPONSE_READ" state was skipped and therefore a proper handshake with the axilite bus wasn't guaranteed.
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- 01 Sep, 2022 1 commit
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Tristan Gingold authored
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- 18 Jul, 2022 1 commit
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Tristan Gingold authored
hdl/sim: Protect CIWBMasterAccessor against multiple requests See merge request !19
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- 16 Jul, 2022 1 commit
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Dimitris Lampridis authored
When performing reads/writes from multiple threads, CIWBMasterAccessor does not provide any protection, leading to data from one request being delivered to another. By replacing the data queues with SV mailboxes, we ensure that only one thread can access the mailbox at any given time. Furthermore, we add a SV event in wb_cycle_t, which is used to notify the readm()/writem() tasks that their transfer is complete, to avoid getting the result of the wrong transfer.
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- 28 Jun, 2022 5 commits
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David Belohrad authored
components purely dependent of xilinx libraries are not compiled in if target differs from xilinx
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David Belohrad authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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