dsp: fix licensing, remove untested/unused/unlicensed code

9a53ab74 · Tomasz Wlostowski · 57ce05b4 · 9a53ab74 · 9a53ab74 · 9a53ab74
Commit 9a53ab74 authored Dec 15, 2022 by Tomasz Wlostowski
15 changed files
--- a/modules/dsp/Manifest.py
+++ b/modules/dsp/Manifest.py
@@ -4,16 +4,11 @@ files = ["cordic_init.vhd",
         "cordic_xy_logic_nhd.vhd",
         "cordic_xy_logic_nmhd.vhd",
         "gc_pipelined_fir_filter.vhd",
-         "gc_averager_decimator.vhd",
         "gc_cordic_pkg.vhd",
         "gc_cordic.vhd",
         "gc_dsp_pkg.vhd",
-         #"gc_frequency_detector.vhd",
-         "gc_iq_amplitude_limiter.vhd",
         "gc_iq_demodulator.vhd",
         "gc_iq_modulator.vhd",
-         "gc_iq_rotate.vhd",
         "gc_pi_regulator.vhd",
-         "gc_rate_limiter.vhd",
         "gc_soft_ramp_switch.vhd",
         "gc_integer_divide.vhd"];
--- a/modules/dsp/cordic_init.vhd
+++ b/modules/dsp/cordic_init.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   cordic_modulo_360.vhd
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Cordic first pipe stage, setting initial values depending on the
+--              function to be calculated.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.STD_LOGIC_1164.all;

--- a/modules/dsp/cordic_modulo_360.vhd
+++ b/modules/dsp/cordic_modulo_360.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   cordic_modulo_360.vhd
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Cordic angle normalization
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
 -- Angle normalization (Mod-360 degree)

 -- If the angle_i argument is greater or smaller than +/-180deg.

--- a/modules/dsp/cordic_xy_logic_hd.vhd
+++ b/modules/dsp/cordic_xy_logic_hd.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   cordic_xy_logic_hd
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Cordic pipeline stage
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/dsp/cordic_xy_logic_nhd.vhd
+++ b/modules/dsp/cordic_xy_logic_nhd.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   cordic_xy_logic_nhd
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Cordic pipeline stage
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/dsp/cordic_xy_logic_nmhd.vhd
+++ b/modules/dsp/cordic_xy_logic_nmhd.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   cordic_xy_logic_nmhd
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Cordic pipeline stage
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/dsp/gc_cordic.vhd
+++ b/modules/dsp/gc_cordic.vhd
 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
+-- CERN SY-RF-FB
 -- General Cores Library
 -- https://www.ohwr.org/projects/general-cores
 --------------------------------------------------------------------------------
 --
 -- unit name:   gc_cordic
 --
-- authors:     fixme
--              
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Fully pipelined multifunction CORDIC code.
 --
 --
 --------------------------------------------------------------------------------

--- a/modules/dsp/gc_cordic_pkg.vhd
+++ b/modules/dsp/gc_cordic_pkg.vhd
 --------------------------------------------------------------------------------
-- (C) Copyright CERN 2014. All rights reserved.
-- This software is released under a CERN proprietary software license.
-- Any permission to use it shall be granted in writing.
-- Requests shall be addressed to CERN through mail-KT@cern.ch
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_cordic_pkg
+--
+-- authors:     Gregoire Hagmann <gregoire.hagmann@cern.ch>
+--              John Molendijk (CERN)
+--
+-- description: Fully pipelined multifunction CORDIC code.
+--
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
 --------------------------------------------------------------------------------

 library ieee;

--- a/modules/dsp/gc_dsp_pkg.vhd
+++ b/modules/dsp/gc_dsp_pkg.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_dsp_pkg
+--
+-- author:      Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+--
+-- description: Shared definitions & types for the DSP core collection.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.All;
 use ieee.numeric_std.All;

--- a/modules/dsp/gc_integer_divide.vhd
+++ b/modules/dsp/gc_integer_divide.vhd
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_integer_divide
+--
+-- author:      Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+--
+-- description: Sequential integer division/remainder unit. Support signed
+--              and unsigned integers.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/dsp/gc_iq_demodulator.vhd
+++ b/modules/dsp/gc_iq_demodulator.vhd
------------------------------------------
------------------------------------------
-- Date        : Sat Jul 11 15:15:22 2015
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
 --
-- Author      : Daniel Valuch
+-- unit name:   gc_iq_demodulator
 --
-- Company     : CERN BE/RF/FB
+-- author:      Gregoire Hagmann <gregoire.hagmann@cern.ch>
 --
-- Description : 
+-- description: Fs/4 IQ demodulator.
 --
------------------------------------------
------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/dsp/gc_iq_modulator.vhd
+++ b/modules/dsp/gc_iq_modulator.vhd
------------------------------------------
------------------------------------------
-- Date        : Fri May 08 16:16:48 2015
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
 --
-- Author      : Gregoire Hagmann
+-- unit name:   gc_iq_modulator
 --
-- Company     : CERN BE-RF
+-- author:      Gregoire Hagmann <gregoire.hagmann@cern.ch>
 --
-- Description : Complex IQ modulator Fs/4
+-- description: Fs/4 IQ modulator.
 --
--  I_i, Q_i : IQ data in baseband
--  Q_o, Q_o : modulated IQ data
--
--  Sync : Synchronization pulse for
--         modulator reset (Cnt=0).
--         1 clk period width
--
--  ModEna: Activation of the modulator
--         '1' : Modulator on
--         '0' : Modulator off
--               (I_o=I_i)
--               (Q_o=Q_i)
--
--  Rst : output reset ('0' output)
--
--  Latency is 2 clk period
--
--  cnt= 0 /  1 /  2 /  3
--  I' = I / -Q / -I /  Q
--  Q' = Q /  I / -Q / -I
------------------------------------------
------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/dsp/gc_pi_regulator.vhd
+++ b/modules/dsp/gc_pi_regulator.vhd
-
+--------------------------------------------------------------------------------
+-- CERN SY-RF-FB
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_pi_regulator.vhd
+--
+-- author:      Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+--
+-- description: Simple PI regulator core with correct limit/overflow handling.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/dsp/gc_pipelined_fir_filter.vhd
+++ b/modules/dsp/gc_pipelined_fir_filter.vhd
 --------------------------------------------------------------------------------
-- CERN BE-CO-HT
+-- CERN SY-RF-FB
 -- General Cores Library
 -- https://www.ohwr.org/projects/general-cores
 --------------------------------------------------------------------------------

--- a/modules/dsp/gc_soft_ramp_switch.vhd
+++ b/modules/dsp/gc_soft_ramp_switch.vhd
-
+--------------------------------------------------------------------------------
+-- CERN BE-CEM-EDL
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name:   gc_soft_ramp_switch
+--
+-- author:      Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+--
+-- description: "soft switch", allowing to raise/squelch a signal slowly
+--              with a programmable rise time and delay. Typical use case is
+--              an on-off switch for LLRF system outputs
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2020
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;