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Platform-independent core collection
Commit d1394507 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbench: update SV Manifests to reflect changes in the naming/files of simulation packages

parent 2c32f3e3
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Showing with 62 additions and 54 deletions
testbench/wishbone/wb_fine_pulse_gen/Manifest.py
View file @ d1394507
......@@ -6,10 +6,10 @@ fetchto = "../../ip_cores"
vcom_opt="-mixedsvvh l -2008"
sim_top="main"
syn_device="xc7k70t"
include_dirs=["../../../sim", "../include" ]
include_dirs=["../../../sim", "../include", "../../../sim/wishbone" ]
modelsim_ini_path="~/eda/modelsim-lib-2016.4"
files = [ "main.sv" ]
modules = { "local" : [ "../../../" ] }
modules = { "local" : [ "../../../", "../../../sim/"] }
testbench/wishbone/wb_fine_pulse_gen/main.sv
View file @ d1394507
......@@ -14,49 +14,19 @@
`timescale 1ps/1ps
`include "vhd_wishbone_master.svh"
`include "wishbone/vhd_wishbone_master.svh"
`include "wb_fine_pulse_gen_regs.vh"
module dupa;
xwb_fine_pulse_gen dut();
endmodule // dupa
`include "glbl.v"
class IBusDevice;
import gencores_sim_pkg::*;
CBusAccessor m_acc;
uint64_t m_base;
function new ( CBusAccessor acc, uint64_t base );
m_acc =acc;
m_base = base;
endfunction // new
virtual task write32( uint32_t addr, uint32_t val );
m_acc.write(m_base +addr, val);
endtask // write
virtual task read32( uint32_t addr, output uint32_t val );
uint64_t val64;
m_acc.read(m_base +addr, val64);
val = val64;
endtask // write
endclass // BusDevice
class FinePulseGenDriver extends IBusDevice;
class FinePulseGenDriver extends CBusDevice;
protected int m_use_delayctrl = 1;
protected real m_coarse_range = 16.0;
protected real m_delay_tap_size = 0.078; /*ns*/
protected int m_fine_taps;
function new(CBusAccessor acc, int base);
super.new(acc,base);
......@@ -69,19 +39,19 @@ class FinePulseGenDriver extends IBusDevice;
$error("Calibrate start");
write32( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_EN_VTC);
write32( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL | `FPG_ODELAY_CALIB_RST_OSERDES | `FPG_ODELAY_CALIB_RST_ODELAY);
writel( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_EN_VTC);
writel( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL | `FPG_ODELAY_CALIB_RST_OSERDES | `FPG_ODELAY_CALIB_RST_ODELAY);
#100ns;
write32( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL | `FPG_ODELAY_CALIB_RST_OSERDES );
writel( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL | `FPG_ODELAY_CALIB_RST_OSERDES );
#100ns;
write32( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL );
writel( `ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_RST_IDELAYCTRL );
#100ns;
write32( `ADDR_FPG_ODELAY_CALIB, 0 );
writel( `ADDR_FPG_ODELAY_CALIB, 0 );
#100ns;
while(1)
begin
read32( `ADDR_FPG_ODELAY_CALIB, rv );
readl( `ADDR_FPG_ODELAY_CALIB, rv );
$display("odelay = %x", rv);
if ( rv & `FPG_ODELAY_CALIB_RDY )
......@@ -89,10 +59,10 @@ class FinePulseGenDriver extends IBusDevice;
end
write32(`ADDR_FPG_ODELAY_CALIB, 0);
write32(`ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_CAL_LATCH);
writel(`ADDR_FPG_ODELAY_CALIB, 0);
writel(`ADDR_FPG_ODELAY_CALIB, `FPG_ODELAY_CALIB_CAL_LATCH);
read32( `ADDR_FPG_ODELAY_CALIB, rv );
readl( `ADDR_FPG_ODELAY_CALIB, rv );
calib_time = real'(1.0);
calib_taps = (rv & `FPG_ODELAY_CALIB_TAPS) >> `FPG_ODELAY_CALIB_TAPS_OFFSET;
......
testbench/wishbone/wb_gpio_port/Manifest.py
View file @ d1394507
......@@ -9,11 +9,13 @@ sim_top = "main" # for hdlmake3
include_dirs = [
"../../../sim/",
"../../../sim/wishbone",
]
modules = {
"local" : [
"../../../",
"../../../sim",
],
}
......
testbench/wishbone/wb_simple_pwm/Manifest.py
View file @ d1394507
sim_tool = "modelsim"
action = "simulation"
target = "xilinx"
fetchto="../../../ip_cores"
fetchto = "../../../ip_cores"
vcom_opt="-mixedsvvh l -2008"
sim_top="main"
syn_device="xc7k70t"
modules = { "local" : "../../../" };
target = "xilinx"
syn_device = "xc6slx45t"
files = ["main.sv"]
top_module = "main" # for hdlmake2
sim_top = "main" # for hdlmake3
vlog_opt= "+incdir+../../../sim"
\ No newline at end of file
include_dirs = [
"../../../sim/",
"../../../sim/wishbone",
]
modules = {
"local" : [
"../../../",
"../../../sim",
],
}
files = [
"main.sv",
]
testbench/wishbone/wb_uart/Manifest.py
View file @ d1394507
sim_tool = "modelsim"
top_module="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
vcom_opt="-mixedsvvh l -2008"
sim_top="main"
syn_device="xc7k70t"
include_dirs=["../../../sim", "../include" ]
files = [ "main.sv" ]
target = "xilinx"
syn_device = "xc6slx45t"
modules = { "local" : [ "../../../" ] }
top_module = "main" # for hdlmake2
sim_top = "main" # for hdlmake3
include_dirs = [
"../../../sim/",
"../../../sim/wishbone",
"../../../sim/regs",
]
modules = {
"local" : [
"../../../",
"../../../sim",
],
}
files = [
"main.sv",
]
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