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  1. Feb 13, 2013
    • Wesley W. Terpstra's avatar
      crossbar: eliminate lexically nested functions · fce11846
      Wesley W. Terpstra authored
      According to Peter Jansweijer, Precision and Questasim had trouble
      synthesizing the crossbar HDL. After tracking the problem down via
      email, it appears that these tools cannot handle nested functions
      correctly; they crash or fail when trying to access the parameters
      of the lexically enclosing function.
      
      Therefore, this patch just outright removes all nested functions.
      fce11846
  2. Feb 11, 2013
  3. Feb 05, 2013
    • Wesley W. Terpstra's avatar
      altera/generic_dpram: Support Arria5 · 39815f08
      Wesley W. Terpstra authored
      Unfortunately, Arria5 cannot do read-old-data for the same port.
      This formulation describes a dual-ported RAM with:
        write-first/read-new-data for RW conflict on same port
        read-first /read-old-data for RW conflict between ports
      ... which is exactly what Arria5 supports (and Arria2 can do too).
      
      Users of the generic_dpram should simply avoid simultaneous
      RW on the same port, as the result is undefined (Altera != Xilinx).
      39815f08
    • Wesley W. Terpstra's avatar
      wb_slave_adapter: rewrote using definition from the B.4 standard. · cda20b67
      Wesley W. Terpstra authored
      The old version didn't do WE properly and was rather strangely coded.
      cda20b67
  4. Jan 28, 2013
    • Wesley W. Terpstra's avatar
      generic_dpram: Should be read-first, as documented. · 904e8886
      Wesley W. Terpstra authored
      Newer quartus versions recognized that the code describes write-first logic,
      which requires combinatorial bypass logic. Unfortunately, this is also impossible
      with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
      RX path failing to synthesize.
      904e8886
  5. Dec 14, 2012
  6. Nov 22, 2012
  7. Nov 16, 2012
    • Wesley W. Terpstra's avatar
      Fully working reverse PCI bridge. · 223ef8de
      Wesley W. Terpstra authored
        * Add an interrupt mask for legacy PCI.
        * Add bits to indicate whether a change to the control register is intended.
        * Made it possible to dequeue an operation without enqueueing an ack/err.
      223ef8de
  8. Nov 15, 2012
    • Wesley W. Terpstra's avatar
      Added interrupt generation as a wishbone interface. · 32323b1c
      Wesley W. Terpstra authored
        * MSI and PCI interrupts in the altera mega-function
        * Restructure master/slave registers for bridge to be more
          readable regarding which address takes which action
        * Receive wishbone operations and use them to pulse interrupts
        * Added registers to indicate the address/data from WB
      32323b1c
  9. Oct 02, 2012
  10. Aug 31, 2012
  11. Aug 29, 2012
  12. Aug 03, 2012
  13. Aug 01, 2012
  14. Jul 10, 2012
  15. Jul 09, 2012
  16. Jul 06, 2012
  17. Jun 21, 2012
  18. Jun 19, 2012
  19. May 25, 2012
  20. May 24, 2012
    • Wesley W. Terpstra's avatar
      Near-complete rewrite of the PCIe-WB4 bridge. · 06d8eacb
      Wesley W. Terpstra authored
      Due to the way Altera uses padding, it is not possible to eliminate it without
      the full state recovered during TLP decoding. Therefore, this version moves
      the padding handling after the 64-32 conversion.
      
      Furthermore, the decoding of TLP records now follows the PCIe 3.0 standard
      instead of the slim Altera documentation. All incoming TLP formats should be
      correctly processed without losing synchronization.
      06d8eacb
    • Wesley W. Terpstra's avatar
      Register reads did not match writes. · b85d3044
      Wesley W. Terpstra authored
      b85d3044
  21. May 22, 2012
  22. May 18, 2012
  23. May 14, 2012
  24. May 08, 2012
  25. May 07, 2012