Near-complete rewrite of the PCIe-WB4 bridge.
Due to the way Altera uses padding, it is not possible to eliminate it without the full state recovered during TLP decoding. Therefore, this version moves the padding handling after the 64-32 conversion. Furthermore, the decoding of TLP records now follows the PCIe 3.0 standard instead of the slim Altera documentation. All incoming TLP formats should be correctly processed without losing synchronization.
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- modules/wishbone/wb_pcie/Manifest.py 2 additions, 0 deletionsmodules/wishbone/wb_pcie/Manifest.py
- modules/wishbone/wb_pcie/pcie_32to64.vhd 49 additions, 0 deletionsmodules/wishbone/wb_pcie/pcie_32to64.vhd
- modules/wishbone/wb_pcie/pcie_64to32.vhd 49 additions, 0 deletionsmodules/wishbone/wb_pcie/pcie_64to32.vhd
- modules/wishbone/wb_pcie/pcie_altera.vhd 65 additions, 141 deletionsmodules/wishbone/wb_pcie/pcie_altera.vhd
- modules/wishbone/wb_pcie/pcie_tlp.vhd 355 additions, 229 deletionsmodules/wishbone/wb_pcie/pcie_tlp.vhd
- modules/wishbone/wb_pcie/pcie_wb.vhd 60 additions, 22 deletionsmodules/wishbone/wb_pcie/pcie_wb.vhd
- modules/wishbone/wb_pcie/pcie_wb_pkg.vhd 37 additions, 10 deletionsmodules/wishbone/wb_pcie/pcie_wb_pkg.vhd
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