Skip to content
Snippets Groups Projects
Commit 8951b79e authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
Browse files

Updated demonstration project files for revised PCIe core.

parent 06d8eacb
Branches
Tags
No related merge requests found
Hide whitespace changes
Inline Side-by-side
syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qsf
+ 2
− 0
View file @ 8951b79e
......@@ -57,6 +57,8 @@ set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_clock_crossin
set_global_assignment -name QIP_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.qip
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_wb.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_64to32.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_32to64.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_tlp.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/pcie_altera.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_pcie/altera_pcie.vhd
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment