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Created with Raphaël 2.2.08Mar529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2127Oct26255423Sep25Jul212019181227Jun211097wb_i2c_bridge: Fix error in state-machineMerge branch 'masterFIP-v1.1.0' into proposed_masterxwb_lm32: expose all PC values for tracinggenrams: expose g_fail_if_init_file_not_found propertytom-masterfiptom-masterfipxwb_crossbar: optimized version with ~4x faster simulation timemodules/common: introduced gc_comparator and accompanying testbench[wishbone] bugfix: new g_sdb_name generic added to wrong entitiy inwrpc-v4.2wrpc-v4.2sdb_crossbar: generate more descriptive SDBno technical change, cleanup copyright holdersupdated manifestgc_sync_ffs: use unique sync chain register name so that a simple constraint can cover all false paths through clock synchronizerswipaxi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridgewishbone/wb_gpio_port: add simple testbenchwishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532common: add default value to master reset in gc_reset. Closes #1628sim: add simple testbench for gc_moving_averagecommon: cleanup gc_moving_average, remove unused signals and ports, drive dout_stb_ocommon: add init values to signals in gc_delay_line to prevent sim warningscommon: add gc_delay_line to Manifest and packagegenrams: make function specifications conform to function bodiescommon: fix component declaration for gc_moving_averagecommon: add missing gc_delay_line.vhd. See also issue #1672sim: import and update bicolor LED controller testbench from SVEC projectxwb_lm32: don't include wr_node/mockturtle profile in the VHDL wrapperwb_axi4lite_bridge: now conforms to AXI4 standardgenrams/xilinx: remove optimizations for ram initializationMerge branch 'greg-vivado' into proposed_masteradding wb to axi4lite bridge by Tomgenrams: ram initialization functions should be impurelm32: fix strip_undefined function for Vivadowb_uart: regenerate wb interface with latest wbgencommon/gc_sync_ffs: add synchronizer attribute for Vivadogenrams/xilinx: speedup RAM initialization for most common widths (mainly for Vivado)genrams/xilinx: split ports to separate processes for Vivado synthesiswb_lm32: remove non synthesizable code when generating lm32_allprofiles.vcommon: added 8b10b decoder coreadding wb to axi4lite bridge by Tomgenrams: ram initialization functions should be impurelm32: fix strip_undefined function for Vivado