They finally don't help much and they break simulation as Modelsim complains
about types conversion.

Peter Jansweijer authored 11 years ago and Grzegorz Daniluk committed 10 years ago

The simulator is crashing at the end of the LM32 startup code when it tries to
access the highest RAM location (at the stack pointer). After this access, the
LM32 verilog code already increments the address to be prepared for the next
cycle, which will never actually happen because you are at the end of the RAM.
It is this address increment in verilog that is one address outside the defined
RAM array for which the simulator complains and terminates. The actual
synthesized code is perfectly fine; no accesses outside RAM.

Grzegorz Daniluk authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources

Replaced by a function taking the number of bits in parameter and returning a vector.

Conflicts:

	modules/genrams/xilinx/Manifest.py

Conflicts:

	modules/genrams/xilinx/Manifest.py
	modules/genrams/xilinx/generic_dpram_sameclock.vhd
	modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd

On Altera, "" generates a null-range warning.
When the dpram is used heavily, these warnings add up to many.

The RW ordering on address conflict varies by platform.
Some platforms only support some options.
Most of the dprams in WR are portable and don't depend on the order.
This new option allows a core to specify that it does not care what
the result of a RW conflict is, and thus work on more platforms.

For Xilinx, "dont_care" = "read_first", the old default.

On both Altera and Xilinx, a dual port memory can achieve twice the
bit-width per memory block when there is a single reader and writer.
This adds a place-holder generic_simple_dpram for Xilinx so that code
using the purpose-built variant for Altera continues to work on ISE.

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.

genrams/xilinx/generic_dpram: made two separate versions for memories with both ports clocked with the same signal and with independent clocks

This is to prevent ISE from interpreting the single-clock template as a dual-clock one, which may result in read-after-write memory content corruption on Spartan-6/Virtex-6 FPGAs.