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Commit 4ff1dac6 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk Committed by Tomasz Wlostowski
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fix almost_full threshold for Virtex6 FIFO

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources
parent e5b971db
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