Grzegorz Daniluk
authored
Xilinx defines almost full threshold not as the used words in the FIFO but as number of available empty words (UG363 - Virtex 6 FPGA Memory Resources
| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| virtex6 | ||
| Manifest.py | ||
| gc_shiftreg.vhd | ||
| generic_dpram.vhd | ||
| generic_dpram_dualclock.vhd | ||
| generic_dpram_sameclock.vhd | ||
| generic_simple_dpram.vhd | ||
| generic_spram.vhd | ||