This is necessary in order to properly "emulate" the previous implementation
of the gc_sync_ffs module.

Furthermore, a "new" module has been introduced, the gc_edge_detect, which
combines positive and negative pulse edge detection. gc_negedge and gc_posedge
have been rewritten to use internally the new gc_edge_detect.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is to avoid any confusion caused by g_SYNC_EDGE and g_EDGE
generics used in gc_sync, gc_sync_ffs and gc_sync_edge modules.

Also use capitals for generics as defined by our coding style.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This generic is dummy (does nothing), yet it is needed since the
generic component declaration in genram_pkg.vhd has such generic.
It has it, because the xilinx generic_dpram.vhd has such generic
and uses it.
TBD whether we want to attempt at providing similar functionality
for altera

Reported by Olof Kindgren (@olofk). See also merge request !4

.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Tomasz Wlostowski authored 5 years ago and Dimitris Lampridis committed 5 years ago

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Reported by Olof Olof Kindgren (@olofk). See also merge request !4

.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This allows them to be used right after in component declarations.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.