genrams/xilinx: address bus modulo ram size but only for simulation
The simulator is crashing at the end of the LM32 startup code when it tries to access the highest RAM location (at the stack pointer). After this access, the LM32 verilog code already increments the address to be prepared for the next cycle, which will never actually happen because you are at the end of the RAM. It is this address increment in verilog that is one address outside the defined RAM array for which the simulator complains and terminates. The actual synthesized code is perfectly fine; no accesses outside RAM.
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