genrams/xilinx: address bus modulo ram size but only for simulation

The simulator is crashing at the end of the LM32 startup code when it tries to
access the highest RAM location (at the stack pointer). After this access, the
LM32 verilog code already increments the address to be prepared for the next
cycle, which will never actually happen because you are at the end of the RAM.
It is this address increment in verilog that is one address outside the defined
RAM array for which the simulator complains and terminates. The actual
synthesized code is perfectly fine; no accesses outside RAM.

modules/genrams/xilinx/generic_dpram_dualclock.vhd

@@ -102,7 +102,15 @@ architecture syn of generic_dpram_dualclock is
   begin
     return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
   end f_file_contents;
-  
+
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
   shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
 
   signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
@@ -130,7 +138,11 @@ begin
     process (clka_i)
     begin
       if rising_edge(clka_i) then
-        qa_o <= ram(to_integer(unsigned(aa_i)));
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+        end if;
         for i in 0 to c_num_bytes-1 loop
           if s_we_a(i) = '1' then
             ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
@@ -143,7 +155,11 @@ begin
     process (clkb_i)
     begin
       if rising_edge(clkb_i) then
-        qb_o <= ram(to_integer(unsigned(ab_i)));
+        if f_is_synthesis then
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
         for i in 0 to c_num_bytes-1 loop
           if s_we_b(i) = '1' then
             ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)

modules/genrams/xilinx/generic_dpram_sameclock.vhd

@@ -102,6 +102,14 @@ architecture syn of generic_dpram_sameclock is
     return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
   end f_file_contents;
 
+  function f_is_synthesis return boolean is
+  begin
+    -- synthesis translate_off
+    return false;
+    -- synthesis translate_on
+    return true;
+  end f_is_synthesis; 
+
   shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
 
   signal s_we_a     : std_logic_vector(c_num_bytes-1 downto 0);
@@ -160,8 +168,13 @@ begin
     process(clk_i)
     begin
       if rising_edge(clk_i) then
-        qa_o <= ram(to_integer(unsigned(aa_i)));
-        qb_o <= ram(to_integer(unsigned(ab_i)));
+        if f_is_synthesis then
+          qa_o <= ram(to_integer(unsigned(aa_i)));
+          qb_o <= ram(to_integer(unsigned(ab_i)));
+        else
+          qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+        end if;
         if(wea_i = '1') then
           ram(to_integer(unsigned(aa_i))) := da_i;
         end if;
@@ -181,13 +194,21 @@ begin
           ram(to_integer(unsigned(aa_i))) := da_i;
           qa_o                            <= da_i;
         else
-          qa_o <= ram(to_integer(unsigned(aa_i)));
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
         end if;
         if(web_i = '1') then
           ram(to_integer(unsigned(ab_i))) := db_i;
           qb_o                            <= db_i;
         else
-          qb_o <= ram(to_integer(unsigned(ab_i)));
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
         end if;
       end if;
 
@@ -203,12 +224,20 @@ begin
         if(wea_i = '1') then
           ram(to_integer(unsigned(aa_i))) := da_i;
         else
-          qa_o <= ram(to_integer(unsigned(aa_i)));
+          if f_is_synthesis then
+            qa_o <= ram(to_integer(unsigned(aa_i)));
+          else
+            qa_o <= ram(to_integer(unsigned(aa_i)) mod g_size);
+          end if;
         end if;
         if(web_i = '1') then
           ram(to_integer(unsigned(ab_i))) := db_i;
         else
-          qb_o <= ram(to_integer(unsigned(ab_i)));
+          if f_is_synthesis then
+            qb_o <= ram(to_integer(unsigned(ab_i)));
+          else
+            qb_o <= ram(to_integer(unsigned(ab_i)) mod g_size);
+          end if;
         end if;
       end if;
     end process;