Matthieu Cattin authored 12 years ago and Tomasz Wlostowski committed 11 years ago

Supports sdb_repo_url and sdb_synthesis records.

sdb-crossbar: add support for meta-information records.
A new generic (g_info) is available to add an array of meta-inforamtion
records to the sdb rom.

sdb-crossbar: add boolean generic to use meta-information records.
Can't find out how to initialise an array with a null-range.

wishbone_pkg: add default value to meta-information generic.

sdb-crossbar: fix conditional constant declaration

sdb-crossbar: use a function to initialise number of info entries constant.

sdb-crossbar: fix syntax error in function.

wishbone_pkg: add embed/extract function for repo-url and synthesis records.

wishbone_pkg: Change some meta-info fields to string and add string manip functions.

wishbone_pkg: Change syn_commit_id type to string.

wishbone_pkg: Fix syntax error.

wishbone_pkg: Fix index bug in string manip functions.

wishbone_pkg: Fix range bug in string manip function.

wishbone_pkg: add integration record support.

sdb-crossbar: Fix range issue with meta-info records.

Conflicts:

	modules/wishbone/wishbone_pkg.vhd

Conflicts:

	modules/wishbone/Manifest.py

common/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart input and combinatorial output to reduce latency

Conflicts:

	modules/common/gc_crc_gen.vhd

Conflicts:

	modules/common/gc_crc_gen.vhd

Conflicts:

	modules/genrams/xilinx/Manifest.py

Conflicts:

	modules/genrams/xilinx/Manifest.py
	modules/genrams/xilinx/generic_dpram_sameclock.vhd
	modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd

Conflicts:

	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd

The LM32 needs a read-enable.
Unfortunately, Xilinx does not have one, so we emulate it.

By using altsyncram directly, we get the follow benefits:
  * clear control of read-write resolution behaviour
  * can specify a mif file for initialization
  * eliminates warnings about dual-port clock inference timings

On Altera, "" generates a null-range warning.
When the dpram is used heavily, these warnings add up to many.

The RW ordering on address conflict varies by platform.
Some platforms only support some options.
Most of the dprams in WR are portable and don't depend on the order.
This new option allows a core to specify that it does not care what
the result of a RW conflict is, and thus work on more platforms.

For Xilinx, "dont_care" = "read_first", the old default.

On both Altera and Xilinx, a dual port memory can achieve twice the
bit-width per memory block when there is a single reader and writer.
This adds a place-holder generic_simple_dpram for Xilinx so that code
using the purpose-built variant for Altera continues to work on ISE.

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.