lm32: use generic_simple_dpram instead of custom memory

The LM32 needs a read-enable.
Unfortunately, Xilinx does not have one, so we emulate it.

modules/wishbone/wb_lm32/Manifest.py

@@ -4,9 +4,9 @@ files = [	"generated/xwb_lm32.vhd",
 				 	"src/jtag_cores.v",
 					"src/lm32_adder.v",
 					"src/lm32_addsub.v",
-					"src/lm32_dp_ram.v",
+					"src/lm32_dp_ram.vhd",
 					"src/lm32_logic_op.v",
-					"src/lm32_ram.v",
+					"src/lm32_ram.vhd",
 					"src/lm32_shifter.v"];
 					
 if(target == "altera"):

modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd

+-- Work-alike to lm32_dp_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_dp_ram is
+  generic(
+    addr_width : natural := 32;
+    addr_depth : natural := 1024;
+    data_width : natural := 8);
+  port(
+    clk_i   : in std_logic;
+    rst_i   : in std_logic;
+    we_i    : in std_logic;
+    waddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    wdata_i : in  std_logic_vector(data_width-1 downto 0);
+    raddr_i : in  std_logic_vector(addr_width-1 downto 0);
+    rdata_o : out std_logic_vector(data_width-1 downto 0));
+end lm32_dp_ram;
+
+architecture syn of lm32_dp_ram is
+
+  constant c_addr_width : natural := f_log2_size(addr_depth);
+
+begin
+
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => addr_depth,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false)
+    port map(
+      clka_i => clk_i,
+      wea_i  => we_i,
+      aa_i   => waddr_i(c_addr_width-1 downto 0),
+      da_i   => wdata_i,
+      clkb_i => clk_i,
+      ab_i   => raddr_i(c_addr_width-1 downto 0),
+      qb_o   => rdata_o);
+  
+end syn;

modules/wishbone/wb_lm32/src/lm32_ram.vhd

+-- Work-alike to lm32_ram.v, but using generic_simple_dpram
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.genram_pkg.all;
+
+entity lm32_ram is
+  generic(
+    data_width    : natural := 1;
+    address_width : natural := 1);
+  port(
+    read_clk      : in  std_logic;
+    write_clk     : in  std_logic;
+    reset         : in  std_logic;
+    enable_read   : in  std_logic;
+    read_address  : in  std_logic_vector(address_width-1 downto 0);
+    enable_write  : in  std_logic;
+    write_address : in  std_logic_vector(address_width-1 downto 0);
+    write_data    : in  std_logic_vector(data_width   -1 downto 0);
+    write_enable  : in  std_logic;
+    read_data     : out std_logic_vector(data_width   -1 downto 0));
+end lm32_ram;
+
+architecture syn of lm32_ram is
+  
+  signal wea : std_logic;
+  signal reb : std_logic;
+  
+  -- Emulate read-enable using another bypass
+  signal old_data : std_logic_vector(data_width-1 downto 0);
+  signal new_data : std_logic_vector(data_width-1 downto 0);
+  signal data     : std_logic_vector(data_width-1 downto 0);
+
+begin
+  
+  wea <= enable_write and write_enable;
+  ram : generic_simple_dpram
+    generic map(
+      g_data_width               => data_width,
+      g_size                     => 2**address_width,
+      g_with_byte_enable         => false,
+      g_addr_conflict_resolution => "write_first",
+      g_dual_clock               => false) -- read_clk always = write_clk in LM32
+    port map(
+      clka_i => read_clk,
+      wea_i  => wea,
+      aa_i   => write_address,
+      da_i   => write_data,
+      clkb_i => write_clk,
+      ab_i   => read_address,
+      qb_o   => new_data);
+  
+  data <= old_data when reb='0' else new_data;
+  read_data <= data;
+  
+  main : process(read_clk) is
+  begin
+    if rising_edge(read_clk) then
+      old_data <= data;
+      reb <= enable_read;
+    end if;
+  end process;
+  
+end syn;