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Platform-independent core collection
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18aa38ce
Commit
18aa38ce
authored
12 years ago
by
Tomasz Wlostowski
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genrams/inferred_sync_fifo: assert full flag one cycle in advance
parent
40f9143d
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modules/genrams/inferred_sync_fifo.vhd
+4
-4
4 additions, 4 deletions
modules/genrams/inferred_sync_fifo.vhd
with
4 additions
and
4 deletions
modules/genrams/inferred_sync_fifo.vhd
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4
−
4
View file @
18aa38ce
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-0
7
-18
-- Last update: 2012-0
9
-18
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -45,7 +45,7 @@ entity inferred_sync_fifo is
g_almost_empty_threshold
:
integer
:
=
0
;
-- threshold for almost empty flag
g_almost_full_threshold
:
integer
:
=
0
;
-- threshold for almost full flag
g_register_flag_outputs
:
boolean
:
=
fals
e
g_register_flag_outputs
:
boolean
:
=
tru
e
);
port
(
...
...
@@ -194,9 +194,9 @@ begin -- syn
empty
<=
'0'
;
end
if
;
if
(
usedw
=
g_size
-
1
and
we_i
=
'1'
and
rd_i
=
'0'
)
then
if
(
usedw
=
g_size
-
2
and
we_i
=
'1'
and
rd_i
=
'0'
)
then
full
<=
'1'
;
elsif
(
rd_i
=
'1'
and
we_i
=
'0'
)
then
elsif
(
usedw
=
g_size
-1
and
rd_i
=
'1'
and
we_i
=
'0'
)
then
full
<=
'0'
;
end
if
;
end
if
;
...
...
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