common/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart...

common/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart input and combinatorial output to reduce latency

Conflicts:

	modules/common/gc_crc_gen.vhd

modules/common/gencores_pkg.vhd

@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2009-09-01
--- Last update: 2012-09-13
+-- Last update: 2012-10-04
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -68,15 +68,17 @@ package gencores_pkg is
       g_half_width              : integer range 2 to 256 := 8;
       g_sync_reset              : integer range 0 to 1   := 1;
       g_dual_width              : integer range 0 to 1   := 0;
-      g_registered_match_output : boolean                := true);
+      g_registered_match_output : boolean                := true;
+      g_registered_crc_output   : boolean                := true);
     port (
-      clk_i   : in  std_logic;
-      rst_i   : in  std_logic;
-      en_i    : in  std_logic;
-      half_i  : in  std_logic;
-      data_i  : in  std_logic_vector(g_data_width - 1 downto 0);
-      match_o : out std_logic;
-      crc_o   : out std_logic_vector(g_polynomial'length - 1 downto 0));
+      clk_i     : in  std_logic;
+      rst_i     : in  std_logic;
+      en_i      : in  std_logic;
+      half_i    : in  std_logic;
+      restart_i : in  std_logic := '0';
+      data_i    : in  std_logic_vector(g_data_width - 1 downto 0);
+      match_o   : out std_logic;
+      crc_o     : out std_logic_vector(g_polynomial'length - 1 downto 0));
   end component;
 
   component gc_moving_average