testbench/wishbone: TB for wb_simple_pwm

testbench/wishbone/wb_simple_pwm/Manifest.py

+action = "simulation"
+target = "xilinx"
+fetchto="../../../ip_cores"
+
+modules = { "local" :  "../../../" };
+
+files = ["main.sv"]
+
+vlog_opt= "+incdir+../../../sim"
\ No newline at end of file

testbench/wishbone/wb_simple_pwm/main.sv

+`timescale 1ns/1ps
+
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"
+
+`include "regs/spwm_regs.vh"
+
+module main;
+
+   reg clk_sys=1, rst_n=0;
+
+   always
+     #5ns clk_sys <= ~clk_sys;
+
+   initial begin 
+      repeat(5) @(posedge clk_sys);
+      rst_n <= 1;
+   end
+   
+
+   IWishboneMaster #(32, 32) U_WB
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+   
+   wb_simple_pwm 
+
+     #(.g_num_channels(8))
+   DUT
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i   (rst_n),
+
+      .wb_adr_i (U_WB.master.adr[5:0]),
+      .wb_dat_i (U_WB.master.dat_o),
+      .wb_dat_o (U_WB.master.dat_i),
+      .wb_cyc_i (U_WB.master.cyc),
+      .wb_stb_i (U_WB.master.stb),
+      .wb_we_i  (U_WB.master.we),
+      .wb_ack_o (U_WB.master.ack),
+      .wb_sel_i (U_WB.master.sel),
+      .wb_stall_o(U_WB.master.stall)
+
+      );
+   
+   
+   initial begin
+      CWishboneAccessor acc;
+      int i;
+      
+      #1000ns;
+      acc = U_WB.get_accessor();
+      acc.set_mode(PIPELINED);
+      U_WB.settings.addr_gran = BYTE;
+
+      
+      acc.write(`ADDR_SPWM_CR, (2 << `SPWM_CR_PRESC_OFFSET) | (254 << `SPWM_CR_PERIOD_OFFSET));
+      
+      acc.write(`ADDR_SPWM_DR0, 0);
+      acc.write(`ADDR_SPWM_DR1, 20);
+      acc.write(`ADDR_SPWM_DR2, 40);
+      acc.write(`ADDR_SPWM_DR3, 127);
+      acc.write(`ADDR_SPWM_DR4, 240);
+      acc.write(`ADDR_SPWM_DR5, 255);
+      
+
+      
+      $stop;
+     
+   end // initial begin
+   
+endmodule // main
+

testbench/wishbone/wb_simple_pwm/run.do

+make
+
+vsim work.main -voptargs="+acc"
+
+do wave.do
+run 30ms
+wave zoomfull
+radix -hex
\ No newline at end of file

testbench/wishbone/wb_simple_pwm/wave.do

+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix hexadecimal /main/DUT/g_num_channels
+add wave -noupdate -radix hexadecimal /main/DUT/g_interface_mode
+add wave -noupdate -radix hexadecimal /main/DUT/g_address_granularity
+add wave -noupdate -radix hexadecimal /main/DUT/clk_sys_i
+add wave -noupdate -radix hexadecimal /main/DUT/rst_n_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_adr_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_dat_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_dat_o
+add wave -noupdate -radix hexadecimal /main/DUT/wb_cyc_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_sel_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_stb_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_we_i
+add wave -noupdate -radix hexadecimal /main/DUT/wb_ack_o
+add wave -noupdate -radix hexadecimal /main/DUT/wb_stall_o
+add wave -noupdate -radix hexadecimal /main/DUT/pwm_o
+add wave -noupdate -radix hexadecimal /main/DUT/drive
+add wave -noupdate -radix hexadecimal /main/DUT/regs_in
+add wave -noupdate -radix hexadecimal /main/DUT/regs_out
+add wave -noupdate -radix hexadecimal /main/DUT/tick
+add wave -noupdate -radix hexadecimal /main/DUT/cntr_pre
+add wave -noupdate -radix hexadecimal /main/DUT/cntr_main
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1409217 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1409154 ps} {1410045 ps}