( trigger output two clock cycles of 40MHz, trigger number on reset line being clocked out at 160MHz)

* Added reset circuitry to DUTInterface_AIDA_rtl.vhd

* Added one extra register of clk4x ( 160MHz ) to aid with timing closure ( although Vivado not reporting negative slack - so have probably got timing contraints wrong :-o )

Hacking around trying to fix problems with IPBus ( DUT interfaces not responding to IPBus , Shutter not responding to IPBus ).
Added rst_ipb signal to syncreg_v block in DUT interfaces and shutter. Added debug.

 Now operates "correctly". Will push to repo, remove debug and try again ( in case debug is accidentally squashing a timing issue ... )

* Stretch FIFO reset in eventBuffer_rtl.vhd

* Incremented version number ( to 16 ) in top_enclustra_tlu_v1e.vhd

* Added a few lines to TLU_enclustra_v1e_setProcessingOrder.tcl to force processing order of XDC file and set VHDL type to 2008 on one file...

* Edited build script to execute a Vivado TCL script in order to set TLU_enclustra_v1e.xdc as "late" processing.

* Hacking on timing constraints in /TLU_enclustra_v1e.xdc
( added TCL command to set TLU_enclustra_v1e.xdc as "late" )

N.B. Also need to edit *.dep files to put TLU_enclustra_v1e.xdc *after* enclustra_ax3_pm3.tcl

After sorting out some of the timing problems now get a firmware image that "works"

The chunk that doesn't work with modern IPBus versions should be harmless

* Bug fixes to enclustra_ax3_pm3_infra.patch ( dos2unix problem )

* Move ipbus_decode_TLUaddrmap.vhd out of the way - since we generate a new one each time

* Increment version number in top_enclustra_tlu_v1e.vhd

* Fixes/improvements to build script build_tlu_firmware.sh

Changed *.dep file to reflect change in repo layout

Putting directory with OHWR as remote repo ( /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/fmc-mtlu/firmware/AIDA_tlu )
into sync with
directory with Github/DavidCussans ( /users/phdgc/tlu-tmp-2018-5-8/work/build/src/firmware_AIDA )

( in with MiniTLU firmware )

Comitting updated schematics for fmc vc . Adding a diagram illustrating coincidence logic. Adding simulation scripts 

test_aida_tlu_trig_counter.py - changed to reflect new address map

Wrote simple firmware to exercise DUT interface pins. Puts out a series of pulses on each pin. See https://elog.phy.bris.ac.uk/elog/AIDA/17 as an example

Wrote a pattern generator function that puts out 0101 pattern then a string of 0. Different number of 01 on different bits

Also, tidying up code and hopefully reducing potential timing-race and meta-stability
issues.

eventFormatter_rtl.vhd