Skip to content

A
AIDA-2020 TLU - Gateware
Commit 60ef1007 authored by David Cussans's avatar David Cussans
Browse files
Options

Wrote simple firmware to exercise DUT interface pins. Puts out a series of… 

Wrote simple firmware to exercise DUT interface pins. Puts out a series of pulses on each pin. See https://elog.phy.bris.ac.uk/elog/AIDA/17 as an example
parent 091e3fce
Hide whitespace changes
Inline Side-by-side
Showing with 381 additions and 7 deletions
hdl/test/fmc_tlu_pin_test.vhd 0 → 100644
View file @ 60ef1007
--=============================================================================
--! @file fmcTlu_pinTest_struct.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL -- VHDL Architecture work.fmcTlu_pinTest.struct
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
--
--! @date 16:18:26 01/24/14
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY fmcTlu_pinTest IS
GENERIC(
g_NUM_DUTS : positive := 3;
g_NUM_TRIG_INPUTS : positive := 4;
g_NUM_EXT_SLAVES : positive := 11; --! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH : positive := 64;
g_IPBUS_WIDTH : positive := 32;
g_NUM_EDGE_INPUTS : positive := 4;
g_SPILL_COUNTER_WIDTH : positive := 12
);
PORT(
cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
reset_i : IN std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic;
-- Signal definitions for TLU in normal use:
--busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
--dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
--triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
--extclk_n_b : INOUT std_logic;
--extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
-- Declare all as outputs for test purposes
busy_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
busy_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
dut_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
spare_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
spare_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
extclk_n_o : OUT std_logic;
extclk_p_o : OUT std_logic --! either external clock in, or a clock being driven out
);
-- Declarations
END ENTITY fmcTlu_pinTest ;
LIBRARY work;
--USE work.ipbus.all;
--USE work.emac_hostbus_decl.all;
--
--USE work.fmcTLU.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ARCHITECTURE struct OF fmcTlu_pinTest IS
-- Architecture declarations
constant c_NUM_OUTPUTS : positive := 6;
signal s_patternData : std_logic_vector( c_NUM_OUTPUTS-1 downto 0);
signal s_reset : std_logic := '0';
signal ipbus_clk : std_logic := '0';
BEGIN
cmp_clks: entity work.clocks_s6_extphy
port map (
sysclk_p => sysclk_p_i,
sysclk_n => sysclk_n_i,
clk_logic_xtal_o=> OPEN,
clko_125 => OPEN,
clko_ipb => ipbus_clk,
locked => leds_o(2),
rsto_125 => OPEN,
rsto_ipb => s_reset,
onehz => leds_o(3)
);
leds_o(1 downto 0) <= ( others => '0');
i2c_scl_b <= 'Z';
i2c_sda_b <= 'Z';
cmp_pattern: entity work.comb_generator
generic map (
g_N_OUTPUT_BITS => c_NUM_OUTPUTS
)
port map (
clk_i => ipbus_clk,
reset_i => s_reset,
data_o => s_patternData
);
gen_duts: for nDut in 0 to g_NUM_DUTS-1 generate
OBUFDS_busy_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => busy_p_o(nDut), -- Diff_p output
OB => busy_n_o(nDut), -- Diff_n output
I => s_patternData(0) -- Buffer input
);
OBUFDS_dut_clk_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => dut_clk_p_o(nDut), -- Diff_p output
OB => dut_clk_n_o(nDut), -- Diff_n output
I => s_patternData(1) -- Buffer input
);
OBUFDS_reset_or_clk_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => reset_or_clk_p_o(nDut), -- Diff_p output
OB => reset_or_clk_n_o(nDut), -- Diff_n output
I => s_patternData(2) -- Buffer input
);
OBUFDS_triggers_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => triggers_p_o(nDut), -- Diff_p output
OB => triggers_n_o(nDut), -- Diff_n output
I => s_patternData(3) -- Buffer input
);
end generate gen_duts;
gen_duts1: for nDut in 1 to g_NUM_DUTS-1 generate
OBUFDS_spare_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => spare_p_o(nDut), -- Diff_p output
OB => spare_n_o(nDut), -- Diff_n output
I => s_patternData(4) -- Buffer input
);
end generate gen_duts1;
OBUFDS_extclk_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => extclk_p_o, -- Diff_p output
OB => extclk_n_o, -- Diff_n output
I => s_patternData(5) -- Buffer input
);
END ARCHITECTURE struct;
scripts/aida_mini_tlu_addr_map.txt~
View file @ 60ef1007
......@@ -6,12 +6,11 @@ DUTMaskW 0x00000020 0xffffffff 0 1
DUTMaskR 0x00000020 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
SerdesRstR 0x00000048 0xffffffff 1 0
ThrCount0R 0x00000049 0xffffffff 1 0
ThrCount1R 0x0000004a 0xffffffff 1 0
ThrCount2R 0x0000004b 0xffffffff 1 0
ThrCount3R 0x0000004c 0xffffffff 1 0
SerdesRst 0x00000040 0xffffffff 1 1
ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
*
* trigger logic = 0x060 **Note the different read and write directions
InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
......
scripts/test_aida_tlu_thresholds.py
View file @ 60ef1007
from PyChipsUser import *
from FmcTluI2c import *
import time
boardIpAddr = "192.168.200.16"
boardPortNum = 50001
......@@ -26,10 +27,13 @@ dacValue = 0xFFFF
print "Setting Vthreshold for all DACs. Code = ", dacValue
boardi2c.set_dac(7,dacValue)
time.sleep(2.0)
dacValue = 0x6000
print "Setting Vthreshold for DAC 0. Code = ", dacValue
boardi2c.set_dac(0,dacValue)
time.sleep(2.0)
# set DACs to -5mV
#boardi2c.set_threshold_voltage(7, -0.005)
boardi2c.set_threshold_voltage(7, -0.005)
ucf/sp605_FMC_mTLU_v1a_pintest.ucf 0 → 100644
View file @ 60ef1007
#
# UCF for version 1a of updated mini-TLU
#
NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K21;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K22;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";
TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
#NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = D17;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = AB4;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = D21;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = W15;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "dip_switch_i[0]" LOC = C18;
NET "dip_switch_i[1]" LOC = Y6;
NET "dip_switch_i[2]" LOC = W6;
NET "dip_switch_i[3]" LOC = E4;
# Ethernet PHY
# Main I2C bus
## C30 on FMC
NET "i2c_scl_b" LOC = T21;
## C31 on FMC
NET "i2c_sda_b" LOC = R22;
#
# I/O to devices under test
## "FMC_LA19_P" , H22 on FMC
NET "busy_p_o[0]" LOC = R11;
## "FMC_LA12_P" , G15 on FMC
NET "busy_p_o[1]" LOC = H13;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_o[2]" LOC = C17;
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9;
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[1]" LOC = C5;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[2]" LOC = B18;
# Remove shutters ( also known as SPARE ) for now
NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_o[0]" LOC = AA10;
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[1]" LOC = V11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_o[2]" LOC = G8;
# Labelled CONT on schematic.
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = V7;
## "FMC_LA07_CC_P" , H13 on FMC
NET "reset_or_clk_p_o[1]" LOC = B2;
## "FMC_LA18_P" , C22 on FMC
NET "reset_or_clk_p_o[2]" LOC = T12;
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
## "FMC_LA32_N" , H38 on FMC
NET "cfd_discr_n_i[0]" LOC = Y18;
## "FMC_LA30_N" , H35 on FMC
NET "cfd_discr_n_i[1]" LOC = AB15;
## "FMC_LA28_N" , H32 on FMC
NET "cfd_discr_n_i[2]" LOC = AB16;
## "FMC_LA24_N" , H29 on FMC
NET "cfd_discr_n_i[3]" LOC = AB14;
## "FMC_LA32_P" , H37 on FMC
NET "cfd_discr_p_i[0]" LOC = W17;
## "FMC_LA30_P" , H34 on FMC
NET "cfd_discr_p_i[1]" LOC = Y15;
## "FMC_LA28_P" , H31 on FMC
NET "cfd_discr_p_i[2]" LOC = AA16;
## "FMC_LA24_P" , H28 on FMC
NET "cfd_discr_p_i[3]" LOC = AA14;
# Threshold comparator outputs
## "FMC_LA33_N" , G37 on FMC
NET "threshold_discr_n_i[0]" LOC = AB17;
## "FMC_LA31_N" , G34 on FMC
NET "threshold_discr_n_i[1]" LOC = V15;
## "FMC_LA29_N" , G31 on FMC
NET "threshold_discr_n_i[2]" LOC = U15;
## "FMC_LA25_N" , G28 on FMC
NET "threshold_discr_n_i[3]" LOC = Y14;
## "FMC_LA33_P" , G36 on FMC
NET "threshold_discr_p_i[0]" LOC = Y17;
## "FMC_LA31_P" , G33 on FMC
NET "threshold_discr_p_i[1]" LOC = U16;
## "FMC_LA29_P" , G30 on FMC
NET "threshold_discr_p_i[2]" LOC = T15;
## "FMC_LA25_P" , G27 on FMC
NET "threshold_discr_p_i[3]" LOC = W14;
############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "extclk_p_o" LOC = H12;
## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
NET "extclk_n_o" LOC = G11;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
## GPIO pins for debugging.
### 1 on J13 (thru series R100 200 ohm)
#NET "gpio_hdr[0]" LOC = N17;
### 3 on J13 (thru series R102 200 ohm)
#NET "gpio_hdr[1]" LOC = M18;
### 5 on J13 (thru series R101 200 ohm)
#NET "gpio_hdr[2]" LOC = A3;
### 7 on J13 (thru series R103 200 ohm)
#NET "gpio_hdr[3]" LOC = L15;
### 2 on J13 (thru series R99 200 ohm)
#NET "gpio_hdr[4]" LOC = F15;
### 4 on J13 (thru series R98 200 ohm)
#NET "gpio_hdr[5]" LOC = B4;
### 6 on J13 (thru series R97 200 ohm)
#NET "gpio_hdr[6]" LOC = F13;
### 8 on J13 (thru series R96 20
#NET "gpio_hdr[7]" LOC = P12;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment