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AIDA-2020 TLU - Gateware
Commit 1bdd615f authored by David Cussans's avatar David Cussans
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Checking in modified build scripts (*.tcl), more work on simulation ( test-bench, pulse generator )

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Introduction.markdown
View file @ 1bdd615f
......@@ -41,8 +41,10 @@ necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
Building Firmware
-----------------
Instructions on building the firmware are found
[here](@ref buildingfirmware).
[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
README.markdown deleted 100755 → 0
View file @ 14eb481d
Firmware for AIDA miniTLU {#buildingfirmware}
=========================
Uses the "IPBus" system to communuicate via Ethernet to host.
Needs Xilinx ISE tools to build. The scripts assume ISE 14.6 or newer.
Needs a licence for the Xilinx Gigabit ethernet soft core (
tri_mode_eth_mac ) if using an external Physical interface chip
(e.g. for "Copper" Ethernet interface).
Needs "IPBus" to communuicate via Ethernet to host.
Scripts developed on a Linux PC. Need to use custom scripts because the
standard Xilinx auto-generated ones "contaminate" directories that are under
version-management control with files generated by core regeneration process.
Firmware build scripts may work under Windows/Cygwin or Windows/MinGW
but not tested.
To build firmware:
1. Install Xilinx ISE 14.6 (or newer) and set up the environment variables.
2. Create a working directory somewhere , <working_directory>
3. <pre> cd <working_directory> </pre>
4. Get a copy of the build scripts:
+ <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/setup_workspace.sh > setup_workspace.sh </pre>
+ <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/build_bitstream.sh > build_bitstream.sh </pre>
+ Edit setup_workspace.sh to reflect which FPGA carrier board you want to build the firmware for.Currently supported boards: Xilinx SP601 , Xilinx SP605 . Default is SP601
5. Execute the script to set-up the ISE project:
<pre> sh setup_workspace.sh </pre>
This will check out copies of the IPBus and AIDA mini-TLU repositories,
create a directory for the files produced by firmware synthesise
and create a Xilinx ISE project file.
6. Produce the bit-stream
+ either:
+ - Open the Xilinx project file at <working_directory>/workspace/fmc-mtlu.xise
+ - Select Tools->COREGEN
+ - When Coregen starts select Project->Upgrade and Regenerate all project IP ( this will take several minutes )
+ - Make sure the top-level file is selected and click on "Generate Programming File"
+ or:
+ - Execute the build_bitstream.sh script.
config/ise14/sp601/build_bitstream.tcl
View file @ 1bdd615f
......@@ -7,7 +7,7 @@ catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
......
config/ise14/sp601/setup_project.tcl
View file @ 1bdd615f
......@@ -68,6 +68,12 @@ xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
......@@ -85,7 +91,7 @@ exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_di
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
xfile add ipcore_dir/CounterUp.xco
# xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
......@@ -107,16 +113,19 @@ xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
#xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
# xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
......
config/ise14/sp605/build_bitstream.tcl
View file @ 1bdd615f
......@@ -7,7 +7,7 @@ catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
......
config/ise14/sp605/setup_project.tcl
View file @ 1bdd615f
......@@ -67,6 +67,11 @@ xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
......@@ -84,7 +89,7 @@ exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_di
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
xfile add ipcore_dir/CounterUp.xco
#xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
......@@ -106,16 +111,18 @@ xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
......
hdl/common/IPBusInterface_rtl.vhd
View file @ 1bdd615f
......@@ -78,7 +78,7 @@ END ENTITY IPBusInterface ;
ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
constant c_NUM_INTERNAL_SLAVES : positive := 2;
constant c_NUM_INTERNAL_SLAVES : positive := 1;
signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
......@@ -194,11 +194,9 @@ BEGIN
-- Slave: firmware ID
firmware_id: entity work.ipbus_ver
port map(
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2)
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
);
-- N.B. Remove port to s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
-- No longer used by hostbus
END ARCHITECTURE rtl;
hdl/common/clocks_s6_extphy.vhd
View file @ 1bdd615f
......@@ -29,7 +29,8 @@ end clocks_s6_extphy;
architecture rtl of clocks_s6_extphy is
signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk , sysclk_in: std_logic;
signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
-- signal sysclk_in : std_logic;
signal d25, d25_d, dcm_locked: std_logic;
signal rst: std_logic := '1';
signal s_xtal_dcm_locked: std_logic;
......
hdl/common/counterWithReset_rtl.vhd
View file @ 1bdd615f
......@@ -59,7 +59,7 @@ END counterWithReset;
ARCHITECTURE rtl OF counterWithReset IS
type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0); -- --! Output registers.
signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0')); -- --! Output registers.
BEGIN
......
hdl/common/dualSERDES_1to4_rtl.vhd
View file @ 1bdd615f
This diff is collapsed.
hdl/common/eventBuffer_rtl.vhd
View file @ 1bdd615f
......@@ -93,6 +93,7 @@ ARCHITECTURE rtl OF eventBuffer IS
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
BEGIN
......@@ -109,10 +110,10 @@ BEGIN
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
s_fifo_dout when "00",
X"0000" & "00" & std_logic_vector(s_fifo_fill_level) when "01",
X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty when "11",
(others => '1') when others;
s_fifo_dout when "00",
s_fifo_fill_level_d1 when "01",
s_fifo_status_ipb when "10",
(others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
......@@ -123,6 +124,11 @@ BEGIN
s_rst_fifo <= '0';
end if;
end if;
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
end process ipbus_write;
-----------------------------------------------------------------------------
......
hdl/common/ipbus_addr_decode.vhd
View file @ 1bdd615f
......@@ -45,8 +45,6 @@ package body ipbus_addr_decode is
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------0000---0-") then
sel := 10; -- version / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------------0000---1-") then
sel := 11; -- emac_hostbus / base 00000002 / mask 00000001
else
sel := 99;
end if;
......
hdl/common/ipbus_ver.vhd
View file @ 1bdd615f
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5e4" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a5ea" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
hdl/common/logic_clocks_rtl.vhd
View file @ 1bdd615f
This diff is collapsed.
hdl/common/triggerInputs_rtl.vhd
View file @ 1bdd615f
......@@ -21,7 +21,43 @@
--! @version v0.1
--
--! @details
--! IPBus address 0 = control and status
--! bit0 = reset serdes
--! bit1 = reset counter
--! bit2 = calibrate IDELAYs
--! bit3 = not connected
--!
--! bit4 = Thresh discr IDelay(0) status prompt
--! bit5 = Thresh discr IDelay(0) status delayed
--! bit6 = Thresh discr IDelay(1) status prompt
--! bit7 = Thresh discr IDelay(1) status delayed
--! bit8 = Thresh discr IDelay(2) status prompt
--! bit9 = Thresh discr IDelay(2) status delayed
--! bit10= Thresh discr IDelay(3) status prompt
--! bit11= Thresh discr IDelay(3) status delayed
--!
--! bit12= CFD discr IDelay(0) status prompt
--! bit13= CFD discr IDelay(0) status delayed
--! bit14= CFD discr IDelay(1) status prompt
--! bit15= CFD discr IDelay(1) status delayed
--! bit16= CFD discr IDelay(2) status prompt
--! bit17= CFD discr IDelay(2) status delayed
--! bit18= CFD discr IDelay(3) status prompt
--! bit19= CFD discr IDelay(3) status delayed
--!
--! bit20= Thresh deserialized data monitor(0)
--! bit21= Thresh deserialized data monitor(1)
--! bit22= Thresh deserialized data monitor(2)
--! bit23= Thresh deserialized data monitor(3)
--! bit24= CFD deserialized data monitor(0)
--! bit25= CFD deserialized data monitor(1)
--! bit26= CFD deserialized data monitor(2)
--! bit27= CFD deserialized data monitor(3)
--!
--! IPBus address 1 = edge rising(0) counter
--! IPBus address 2 = edge rising(1) counter
--! IPBus address 3 = edge rising(2) counter
--! IPBus address 4 = edge rising(3) counter
--!
--! <b>Dependencies:</b>\n
--!
......@@ -85,7 +121,7 @@ END ENTITY triggerInputs ;
--
ARCHITECTURE rtl OF triggerInputs IS
signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and calibrate IODELAY
signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); --! inputs from comparator
......@@ -95,8 +131,6 @@ ARCHITECTURE rtl OF triggerInputs IS
type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
signal s_serdes_reset : std_logic := '0'; --! Take high to reset serdes and initiate IODELAY calibration
signal s_cfd_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
signal s_CFD_rising_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
......@@ -116,8 +150,8 @@ ARCHITECTURE rtl OF triggerInputs IS
constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
signal s_reset_serdes_reg : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_counter_reset: std_logic := '0';
-- signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
BEGIN
......@@ -135,32 +169,43 @@ BEGIN
reset => ipbus_reset_i ,
ipbus_in => ipbus_i,
ipbus_out => ipbus_o,
d=> s_status_to_ipbus,
d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb => open
);
-- sync data from I/O logic to IPBus
sync_registers: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic,
data_i => s_status_to_ipbus,
data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
-- sync data from I/O logic to IPBus
sync_ipbus: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_CTRL )
port map (
clk_input_i => ipbus_clk_i,
data_i => s_control_from_ipbus,
data_o => s_sync_control_from_ipbus,
clk_output_i => clk_4x_logic);
-- Map the control registers...
-- Register that controls IODELAY and ISERDES reset is at address 0
-- temporarily disable control signals ( need to register them to aid timing
-- closure... )
--s_reset_serdes_reg <= s_control_from_ipbus(0);
--s_rst_iserdes <= s_reset_serdes_reg(0);
--s_counter_reset <= s_reset_serdes_reg(1);
--s_reset_serdes_reg <= '0';
s_rst_iserdes <= '0';
s_counter_reset <= '0';
s_rst_iserdes <= s_sync_control_from_ipbus(0)(0);
s_counter_reset <= s_sync_control_from_ipbus(0)(1);
s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
s_status_to_ipbus(0)(0) <= s_rst_iserdes;
s_status_to_ipbus(0)(1) <= s_counter_reset;
s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
-- Connect up unused lines in status regiser to 0.
s_status_to_ipbus(0)(3) <= '0';
s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
-----------------------------------------------------------------------------
-- Connect up trigger inputs to deserializers and a LUT to determine
-- arrival time
......@@ -181,12 +226,14 @@ BEGIN
thresholdDeserializer: entity work.dualSERDES_1to4
port map (
serdes_reset_i => s_rst_iserdes,
reset_i => s_rst_iserdes,
calibrate_i => s_calibrate_idelay,
data_i => s_threshold_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_threshold_data(triggerInput)
data_o => s_deserialized_threshold_data(triggerInput),
status_o => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
);
s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
......@@ -227,12 +274,14 @@ BEGIN
CFDDeserializer: entity work.dualSERDES_1to4
port map (
serdes_reset_i => s_rst_iserdes,
reset_i => s_rst_iserdes,
calibrate_i => s_calibrate_idelay,
data_i => s_CFD_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
data_o => s_deserialized_CFD_data(triggerInput)
data_o => s_deserialized_CFD_data(triggerInput),
status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
);
s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
......@@ -253,6 +302,13 @@ BEGIN
if rising_edge(clk_4x_logic) then
s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
-- Monitor output of serdes - just look at one per serdes
-- Don't care about latency so put a couple of registers in to aid
-- timing closure.
s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
end if ;
end process;
......@@ -271,7 +327,10 @@ BEGIN
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
--! Monitor output of deserializer
-- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_status_to_ipbus(0)(23 downto 20);
trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
END ARCHITECTURE rtl;
hdl/test/clock_divider_s6.v
View file @ 1bdd615f
......@@ -9,7 +9,8 @@ module clock_divider_s6(
wire [6:0] q;
reg [5:0] qr = 0;
reg [2:0] ctr = 0;
//wire unconnected; // horrid hack
assign q[0] = 1'b1;
generate
......
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
View file @ 1bdd615f
......@@ -16,9 +16,12 @@ PACKAGE fmcTLU IS
constant c_NUM_TIME_BITS : natural := 5;
constant c_NUM_TRIG_INPUTS : natural := 4;
constant c_EVENT_DATA_WIDTH : natural := 32;
constant c_DATA_WIDTH : natural := 32;
--subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
--type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
END fmcTLU;
hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ 1bdd615f
......@@ -47,8 +47,8 @@ ENTITY top_extphy IS
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
extclk_n_b : INOUT std_logic;
extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic;
extclk_p_b : OUT std_logic; --! either external clock in, or a clock being driven out
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
......@@ -287,8 +287,8 @@ ARCHITECTURE struct OF top_extphy IS
ipbus_o : OUT ipb_rbus ;
strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic ;
extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic ;
clk_logic_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
......
scripts/FmcTluI2c.py
View file @ 1bdd615f
......@@ -88,7 +88,7 @@ class FmcTluI2c:
#################
### set DAC value
#################
def set_dac(self,channel,value):
def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
if channel<0 or channel>7:
print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
......@@ -96,10 +96,17 @@ class FmcTluI2c:
print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
return -1
# AD5665R chip with A0,A1 tied to ground
i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
#i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
# enter vref-on mode:
dac.write([0x38,0x00,0x01])
# if we want to enable internal voltage reference:
if vrefOn:
# enter vref-on mode:
print "Turning internal reference ON"
dac.write([0x38,0x00,0x01])
else:
print "Turning internal reference OFF"
dac.write([0x38,0x00,0x00])
# now set the actual value
sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
print sequence
......@@ -110,13 +117,20 @@ class FmcTluI2c:
##################################################
### convert required threshold voltage to DAC code
##################################################
# WARNING THIS CODE IS BUGGY.
def convert_voltage_to_dac(self,desiredVoltage):
Vref = 2.50
def convert_voltage_to_dac(self,desiredVoltage, Vref=1.300):
Vdaq = ( desiredVoltage + Vref ) / 2
dacCode = 0xFFFF * Vdaq / Vref
return int(dacCode)
##################################################
### calculate the DAC code required and set DAC
##################################################
def set_threshold_voltage(self, channel , voltage ):
dacCode = self.convert_voltage_to_dac(voltage)
print " requested voltage, calculated DAC code = " , voltage , dacCode
self.set_dac(channel , dacCode)
scripts/aida_mini_tlu_addr_map.txt
View file @ 1bdd615f
......@@ -4,7 +4,11 @@ FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
*
* trigger inputs = 0x040
SerdesRst 0x00000040 0xffffffff 0 1
SerdesRst 0x00000040 0xffffffff 1 1
ThrCount0 0x00000041 0xffffffff 1 0
ThrCount1 0x00000042 0xffffffff 1 0
ThrCount2 0x00000043 0xffffffff 1 0
ThrCount3 0x00000044 0xffffffff 1 0
*
* trigger logic = 0x060
PostVetoTriggers 0x00000060 0xffffffff 1 0
......
scripts/setup.sh deleted 100755 → 0
View file @ 14eb481d
#!/bin/sh
#
# Script to build firmware for FMC-based AIDA mini-TLU
#
# Create a working directory and execute this script....
export FW_WORKSPACE=`pwd`
echo "Current directory = " $FW_WORKSPACE
export BOARD_TYPE=sp601
export ISE_VER=ise14
# Check out FMC-MTLU code
TLUDir=`pwd`/fmc-mtlu
if [ ! -d "$TLUDir" ]; then
echo "Checking out CBC code"
mkdir fmc-mtlu
pushd fmc-mtlu
svn co http://svn.ohwr.org/fmc-mtlu/trunk/firmware
popd
echo "Checked out FMC-MTLU code"
fi
# Check out IPBus code
IPBusDir=`pwd`/IPBus2
if [ ! -d "$IPBusDir" ]; then
mkdir $IPBusDir
pushd $IPBusDir
svn co http://svn.cern.ch/guest/cactus/tags/ipbus_2_0_v1/firmware
echo "Checked out IPBus2 code"
popd
fi
# Check out directory for external cores ( e.g. I2C)
if [ ! -d "external" ]; then
echo "Checking out I2C code"
svn co http://cactus.hepforge.org/svn/tags/firmware_pre_131_RAL/firmware/external
fi
# Create a directory contain the build products.
WorkDir=workspace
if [ ! -d "$WorkDir" ]; then
mkdir workspace
mkdir workspace/ipcore_dir
echo "Made workspace"
fi
export REPOS_BUILD_DIR=`pwd`/workspace
pushd workspace
# Create soft links to ipbus, fmc-mtlu code , i2c code
if [ ! -e "ipbus" ]; then
ln -s $IPBusDir ipbus
fi
if [ ! -e "fmc-mtlu" ]; then
ln -s ../fmc-mtlu .
fi
if [ ! -e "external" ]; then
ln -s ../external .
fi
if [ ! -e "file_list" ]; then
ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
fi
if [ ! -e "ipbus" ]; then
ln -s ../$IPBusDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
fi
pushd ipcore_dir
if [ ! -e "coregen.cgp" ]; then
ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/coregen.cgp .
fi
popd
#export REPOS_FW_DIR=$IPBusDir
export REPOS_FW_DIR=ipbus
echo "IPBus directory = " $IPBusDir
echo "FMC-MTLU directry = " $TLUDir
xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/setup_project.tcl
echo "Finished setting up ISE project. Open in $ISE_VER and build bit-stream"
scripts/test_aida_tlu_thresholds.py
View file @ 1bdd615f
......@@ -14,13 +14,22 @@ boardi2c = FmcTluI2c(board)
boardFirmware = board.read("FirmwareId")
print "Firmware version = " , hex(boardFirmware)
#scanResults = boardi2c.i2c_scan()
#print scanResults
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
# Set thresholds at about -0.1V ( with 1MOhm f/back resistors )
print "Setting Vthreshold to about -0.1V"
boardi2c.set_dac(7,0x4100)
#dacValue = 0x4100
dacValue = 0xFFFF
print "Setting Vthreshold for all DACs. Code = ", dacValue
boardi2c.set_dac(7,dacValue)
dacValue = 0x6000
print "Setting Vthreshold for DAC 0. Code = ", dacValue
boardi2c.set_dac(0,dacValue)
# set DACs to -5mV
#boardi2c.set_threshold_voltage(7, -0.005)
scripts/test_aida_tlu_trig_counter.py 0 → 100644
View file @ 1bdd615f
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
boardIpAddr = "192.168.200.16"
boardPortNum = 50001
addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
boardFirmware = board.read("FirmwareId")
print "Firmware version = " , hex(boardFirmware)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 1
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.200)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
#print "Setting PLL input to ext. clk"
#board.write("LogicRst", 0 )
#clockStatus = board.read("LogicClocksCSR")
#print "Clock status = " , hex(clockStatus)
inputStatus = board.read("SerdesRst")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRst", 0x00000003 )
inputStatus = board.read("SerdesRst")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRst", 0x00000000 )
inputStatus = board.read("SerdesRst")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRst", 0x00000004 )
inputStatus = board.read("SerdesRst")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRst", 0x00000000 )
inputStatus = board.read("SerdesRst")
print "Input status after calibration = " , hex(inputStatus)
# Look at status of input IODELAYs
numLoops = 5
for iLoop in range(0,numLoops):
inputStatus = board.read("SerdesRst")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0")
print " Count 0 = " , count0
count1 = board.read("ThrCount1")
print " Count 1 = " , count1
count2 = board.read("ThrCount2")
print " Count 2 = " , count2
count3 = board.read("ThrCount3")
print " Count 3 = " , count3
time.sleep(1.0)
simulation/questa/fmctlu_v0_1_testbench.fdo 0 → 100644
View file @ 1bdd615f
######################################################################
##
## Filename: fmctlu_v0_1_testbench.fdo
## Created on: Fri Feb 28 10:49:46 GMT 2014
##
## Auto generated by Project Navigator for Behavioral Simulation
##
## ---------------------DO NOT EDIT THIS FILE-------------------------
## You may want to add additional commands to control the simulation
## in the user specific do file (<module>.udo) which is automatically
## generated in the project directory and will not be removed on
## subsequent simulation flows run from Project Navigator.
## ---------------------DO NOT EDIT THIS FILE-------------------------
##
######################################################################
#
# Create work library
#
vlib work
#
# Compile sources
#
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_if.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd"
vcom -explicit -93 "ipbus/firmware/example_designs/hdl/clock_div.vhd"
vcom -explicit -93 "ipcore_dir/tri_mode_eth_mac_v5_4.vhd"
vcom -explicit -93 "ipcore_dir/mac_fifo_axi4.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/trans_arb.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/stretcher.vhd"
vcom -explicit -93 "ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd"
vcom -explicit -93 "external/opencores_i2c/i2c_master_registers.vhd"
vcom -explicit -93 "external/opencores_i2c/i2c_master_byte_ctrl.vhd"
vcom -explicit -93 "external/opencores_i2c/i2c_master_bit_ctrl.vhd"
vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd"
vlog "../fmc-mtlu/firmware/hdl/test/clock_divider_s6.v"
vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd"
vcom -explicit -93 "ipcore_dir/tlu_event_fifo.vhd"
vcom -explicit -93 "ipcore_dir/internalTriggerGenerator.vhd"
vcom -explicit -93 "ipcore_dir/FIFO.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd"
vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd"
vcom -explicit -93 "ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd"
vcom -explicit -93 "external/opencores_i2c/i2c_master_top.vhd"
vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd"
vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd"
vcom -explicit -93 "fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd"
vlog "/automount/users/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//verilog/src/glbl.v"
#
# Call vsim to invoke simulator
#
vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.fmctlu_v0_1_testbench glbl
#
# Source the wave do file
#
do {fmctlu_v0_1_testbench_wave.fdo}
#
# Set the window types
#
view wave
view structure
view signals
#
# Source the user do file
#
do {fmctlu_v0_1_testbench.udo}
#
# Run simulation for this time
#
run 1000ns
#
# End
#
simulation/questa/fmctlu_v0_1_testbench.udo 0 → 100644
View file @ 1bdd615f
######################################################################
##
## Filename: fmctlu_v0_1_testbench.udo
## Created on: Wed Feb 26 17:46:18 GMT 2014
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
simulation/questa/fmctlu_v0_1_testbench_wave.fdo 0 → 100644
View file @ 1bdd615f
######################################################################
##
## Filename: fmctlu_v0_1_testbench_wave.fdo
## Created on: Wed Feb 26 17:46:21 GMT 2014
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
# add wave /glbl/GSR
simulation/questa/modelsim.ini 0 → 100644
View file @ 1bdd615f
This diff is collapsed.
simulation/scripts/addfiles_sim.tcl 0 → 100644
View file @ 1bdd615f
# Horrible hacky TCL script to build ISE project from hierarchy of source lists
proc dofile {f} {
set fp [open $f r]
set files [read $fp]
close $fp
foreach f_line [split $files "\n"] {
if {$f_line == "" || [string index $f_line 0] == "#"} {
continue
}
set l [split $f_line]
set cmd [lindex $l 0]
set arg1 [lindex $l 1]
set arg2 [lindex $l 2]
set f_list [glob $::env(REPOS_FW_DIR)/$arg1]
foreach f_loc $f_list {
set f_loc_s [exec basename $f_loc]
if {$cmd == "hdl"} {
addfile $f_loc $arg2
} elseif {$cmd == "core"} {
addcore $f_loc $arg2
} elseif {$cmd == "include"} {
dofile $f_loc
}
}
}
}
proc addfile {f lib} {
project addfile $f
}
proc addcore {f lib} {
addfile [file rootname $f].vhd $lib
}
dofile $::env(REPOS_BUILD_DIR)/file_list
simulation/scripts/file_list 0 → 100644
View file @ 1bdd615f
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
hdl $FW_WORKSPACE/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
hdl $FW_WORKSPACE/workspace/ipcore_dir/mac_fifo_axi4.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_registers.vhd
hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
hdl $FW_WORKSPACE/workspace/ipcore_dir/tlu_event_fifo.vhd
hdl $FW_WORKSPACE/workspace/ipcore_dir/internalTriggerGenerator.vhd
hdl $FW_WORKSPACE/workspace/ipcore_dir/FIFO.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_top.vhd
hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
simulation/scripts/setup.sh 0 → 100644
View file @ 1bdd615f
#!/bin/sh
export MODELSIM_ROOT="/software/CAD/Mentor/2013_2014/Questa/HDS_2012.2b/questasim/"
export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/"
export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/"
vsim -c -do $REPOS_FW_DIR/ipbus/firmware/sim/scripts/setup_project.tcl
cp -r $REPOS_FW_DIR/ipbus/firmware/ethernet/sim/modelsim_fli ./
cd modelsim_fli
./mac_fli_compile.sh
cd ..
ln -s modelsim_fli/mac_fli.so
simulation/scripts/setup_project.tcl 0 → 100644
View file @ 1bdd615f
# Creates a new Questa project for ipbus demo
#
# You will want to amend the path to compiled Xilinx libraries to suit
# your system.
#
# Dave Newbold, April 2011
#
# $Id$
set xlib_vhdl $::env(ISE_VHDL_MTI)
set xlib_vlog $::env(ISE_VLOG_MTI)
project new ./ ipbus_sim_demo
vmap unisim $xlib_vhdl/unisim
vmap unimacro $xlib_vhdl/unimacro
vmap secureip $xlib_vlog/secureip
vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
source $::env(REPOS_FW_DIR)/ipbus/firmware/sim/scripts/addfiles_sim.tcl
project calculateorder
project close
quit
simulation_src/fmc-tlu_v0-1_test-bench.vhd 0 → 100644
View file @ 1bdd615f
--=============================================================================
--! @file fmc-tlu_v0-1_test-bench.vhd
--=============================================================================
--! @brief Test-bench for FMC format mini-TLU for AIDA
--
--! @details
--
--! @author David Cussans, 31/07/12
--! @date 11:49:20 02/21/2014
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fmctlu_v0_1_testbench IS
END fmctlu_v0_1_testbench;
ARCHITECTURE behavior OF fmctlu_v0_1_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_extphy
PORT(
busy_n_i : IN std_logic_vector(2 downto 0);
busy_p_i : IN std_logic_vector(2 downto 0);
cfd_discr_n_i : IN std_logic_vector(3 downto 0);
cfd_discr_p_i : IN std_logic_vector(3 downto 0);
dip_switch_i : IN std_logic_vector(3 downto 0);
dut_clk_n_i : IN std_logic_vector(2 downto 0);
dut_clk_p_i : IN std_logic_vector(2 downto 0);
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector(7 downto 0);
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector(3 downto 0);
threshold_discr_p_i : IN std_logic_vector(3 downto 0);
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector(7 downto 0);
gpio_hdr : OUT std_logic_vector(7 downto 0);
leds_o : OUT std_logic_vector(3 downto 0);
phy_rstb_o : OUT std_logic;
reset_or_clk_n_o : OUT std_logic_vector(2 downto 0);
reset_or_clk_p_o : OUT std_logic_vector(2 downto 0);
triggers_n_o : OUT std_logic_vector(2 downto 0);
triggers_p_o : OUT std_logic_vector(2 downto 0);
extclk_n_b : INOUT std_logic;
extclk_p_b : INOUT std_logic;
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
END COMPONENT;
--Inputs
signal busy_n_i : std_logic_vector(2 downto 0) := (others => '0');
signal busy_p_i : std_logic_vector(2 downto 0) := (others => '0');
signal cfd_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
signal cfd_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
signal dip_switch_i : std_logic_vector(3 downto 0) := (others => '0');
signal dut_clk_n_i : std_logic_vector(2 downto 0) := (others => '0');
signal dut_clk_p_i : std_logic_vector(2 downto 0) := (others => '0');
signal gmii_rx_clk_i : std_logic := '0';
signal gmii_rx_dv_i : std_logic := '0';
signal gmii_rx_er_i : std_logic := '0';
signal gmii_rxd_i : std_logic_vector(7 downto 0) := (others => '0');
signal sysclk_n_i : std_logic := '0';
signal sysclk_p_i : std_logic := '0';
signal threshold_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
signal threshold_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
signal s_threshold_discr : std_logic_vector(3 downto 0) := (others => '0');
--BiDirs
signal extclk_n_b : std_logic;
signal extclk_p_b : std_logic;
signal i2c_scl_b : std_logic;
signal i2c_sda_b : std_logic;
--Outputs
signal gmii_gtx_clk_o : std_logic;
signal gmii_tx_en_o : std_logic;
signal gmii_tx_er_o : std_logic;
signal gmii_txd_o : std_logic_vector(7 downto 0);
signal gpio_hdr : std_logic_vector(7 downto 0);
signal leds_o : std_logic_vector(3 downto 0);
signal phy_rstb_o : std_logic;
signal reset_or_clk_n_o : std_logic_vector(2 downto 0);
signal reset_or_clk_p_o : std_logic_vector(2 downto 0);
signal triggers_n_o : std_logic_vector(2 downto 0);
signal triggers_p_o : std_logic_vector(2 downto 0);
signal sysclock : std_logic := '0';
constant sysclock_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_extphy PORT MAP (
busy_n_i => busy_n_i,
busy_p_i => busy_p_i,
cfd_discr_n_i => cfd_discr_n_i,
cfd_discr_p_i => cfd_discr_p_i,
dip_switch_i => dip_switch_i,
dut_clk_n_i => dut_clk_n_i,
dut_clk_p_i => dut_clk_p_i,
gmii_rx_clk_i => gmii_rx_clk_i,
gmii_rx_dv_i => gmii_rx_dv_i,
gmii_rx_er_i => gmii_rx_er_i,
gmii_rxd_i => gmii_rxd_i,
sysclk_n_i => sysclk_n_i,
sysclk_p_i => sysclk_p_i,
threshold_discr_n_i => threshold_discr_n_i,
threshold_discr_p_i => threshold_discr_p_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
gmii_tx_en_o => gmii_tx_en_o,
gmii_tx_er_o => gmii_tx_er_o,
gmii_txd_o => gmii_txd_o,
gpio_hdr => gpio_hdr,
leds_o => leds_o,
phy_rstb_o => phy_rstb_o,
reset_or_clk_n_o => reset_or_clk_n_o,
reset_or_clk_p_o => reset_or_clk_p_o,
triggers_n_o => triggers_n_o,
triggers_p_o => triggers_p_o,
extclk_n_b => extclk_n_b,
extclk_p_b => extclk_p_b,
i2c_scl_b => i2c_scl_b,
i2c_sda_b => i2c_sda_b
);
-- Clock process definitions
sysclock_process :process
begin
sysclock <= '0';
wait for sysclock_period/2;
sysclock <= '1';
wait for sysclock_period/2;
end process;
sysclk_n_i <= not sysclock;
sysclk_p_i <= sysclock;
-- Generate pulses
cmp_pulseGen: entity work.pmtPulseGenerator
generic map (
g_NUM_CHANNELS => 4)
port map (
pulses_o => s_threshold_discr,
numPulses_i => 50,
averagePulseInterval_i => 10 us,
averagePulseWidth_i => 10 ns,
pulseJitter_i => 2 ns,
sysclock_i => sysclock,
simulationDone_o => open);
threshold_discr_p_i <= s_threshold_discr;
threshold_discr_n_i <= not s_threshold_discr;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for sysclock_period*10;
-- insert stimulus here
wait;
end process;
END;
simulation_src/pmtPulseGenerator_rtl.vhd 0 → 100644
View file @ 1bdd615f
--=============================================================================
--! @file pmtPulseGenerator_rtl.vhd
--=============================================================================
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
-------------------------------------------------------------------------------
-- VHDL Architecture pmtPulseGenerator.rtl
--
--! @brief Produce a series of random pulses. Timing can be optionally
--! referered to system clock.
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--!
--
--! @date 4/3/14
--
--! @version v0.1
--
--! @details
--!
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by: </b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.Math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
entity pmtPulseGenerator is
generic (
g_NUM_CHANNELS : positive := 4); -- --! Number of signal lines
port (
pulses_o : out std_logic_vector(g_NUM_CHANNELS-1 downto 0); --! Output pulses
-- pulseRecord_o : out t_pulseRecord ; --! Record describing the output pulses
numPulses_i : in positive; --! Number of pulses/events to generate
averagePulseInterval_i : in time; --! Mean interval between pulses
averagePulseWidth_i : in time; --! Mean pulse width (must be smaller than interval)
pulseJitter_i : in time; --! Time spread between outputs.
sysclock_i : in std_logic; -- --! Pulses can be optionally referred to rising edge
simulationDone_o : out boolean --! Goes high when pulse generation is finished
);
end pmtPulseGenerator;
ARCHITECTURE behavior OF pmtPulseGenerator IS
signal s_masterPulse : std_logic := '0';
BEGIN
-- Generate "master" pulse
stim_proc: process
variable v_seed1 : POSITIVE := 28;
variable v_seed2 : POSITIVE := 17;
variable v_pulseWidth , v_pulseLow : time ;
variable Rand : real;
begin
assert ( averagePulseInterval_i > averagePulseWidth_i ) report "Pulse width can't be larger than pulse interval!!" severity failure;
simulationDone_o <= False;
s_masterPulse <= '0';
for I in 1 to numPulses_i loop
-- wait for random gap between pulses
uniform(v_seed1, v_seed2, Rand);
v_pulseLow := Rand * (averagePulseInterval_i - averagepulseWidth_i);
wait for v_pulseLow;
s_masterPulse <= '1'; --! Take pulse high.
-- wait for random pulse width
uniform(v_seed1, v_seed2, Rand);
v_pulseWidth := Rand * averagePulseWidth_i;
wait for v_pulseWidth;
s_masterPulse <= '0'; --! Return pulse low.
end loop;
simulationDone_o <= True;
wait;
end process;
--! Generate separate outputs that follow the main pulse with timing jitter.
gen_PulseOutputs: for v_output in 0 to g_NUM_CHANNELS-1 generate
-- purpose: Sets the individual output pulses based on master pulse
-- output: pulses_o(v_output)
p_setOutputs: process
variable v_timeOffset : time := 0 ns; -- --! offset between master pulse changing and output changing.
variable Rand : real;
variable v_seed1 : POSITIVE := 19*(v_output+1);
variable v_seed2 : POSITIVE := 47*(v_output+1);
begin -- process p_setOutputs
-- set the output low
-- pulses_o(v_output) <= '0';
wait on s_masterPulse;
if rising_edge(s_masterPulse) then
--report "Pulse output proc: found rising edge" severity note;
-- Generate some jitter
uniform(v_seed1, v_seed2, Rand);
v_timeOffset := Rand * pulseJitter_i;
--report "Pulse output proc: waiting to set output pulse" severity note;
-- wait for that jitter
wait for v_timeOffset;
-- set the output high
pulses_o(v_output) <= '1';
else
-- falling edge....
-- wait for jitter time
wait for v_timeOffset;
-- return the output low.
pulses_o(v_output) <= '0';
end if;
end process p_setOutputs;
end generate gen_PulseOutputs;
END;
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