Removed unused logic. Tidied up formatting. Changed version number

a8cb830a · David Cussans · d3f83532 · a8cb830a · a8cb830a · a8cb830a
Commit a8cb830a authored Nov 21, 2014 by David Cussans
Showing with 66 additions and 88 deletions

eventBuffer_rtl.vhd hdl/common/eventBuffer_rtl.vhd +3 -29

eventFormatter_rtl.vhd hdl/common/eventFormatter_rtl.vhd +62 -58

ipbus_ver.vhd hdl/common/ipbus_ver.vhd +1 -1

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--- a/hdl/common/eventBuffer_rtl.vhd
+++ b/hdl/common/eventBuffer_rtl.vhd
@@ -80,12 +80,8 @@ END ENTITY eventBuffer ;
 ARCHITECTURE rtl OF eventBuffer IS


-  -- write addr count width = 13 , read addr count = 14.
-  --! Counters for input and ouput to/from FIFO
-  signal s_wr_data_count , s_wr_data_count_reg  : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');  
  signal s_rd_data_count    : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');

-  --signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');  -- read-counter - 2*write_count
  signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0');  -- read-counter - 2*write_count
  
  signal s_write_strobe    : std_logic := '0';
@@ -105,7 +101,7 @@ BEGIN

  --! Generate FIFO read enable
  s_fifo_rd_en  <= '1' when ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" else '0';
-	s_fifo_valid <= '1';
+  s_fifo_valid <= '1';
 	
  --! Generate IPBus ACK 
  ipbus_o.ipb_ack <= (ipbus_i.ipb_strobe and not s_fifo_rd_en) or (s_fifo_valid and s_fifo_rd_en);
@@ -127,9 +123,8 @@ BEGIN
      end if;

    -- Register data onto IPBus clock domain to ease timing closure.
-    s_fifo_status_ipb <=  X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
-    --s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
-	 s_fifo_fill_level <= X"0000" & s_rd_data_count; 
+      s_fifo_status_ipb <=  X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+      s_fifo_fill_level <= X"0000" & s_rd_data_count; 
    end if;
  end process ipbus_write;
  
@@ -155,31 +150,10 @@ BEGIN
    empty => s_fifo_empty,
    almost_empty => s_fifo_almost_empty,
    rd_data_count => s_rd_data_count,
-    wr_data_count => s_wr_data_count,
    prog_full => s_fifo_prog_full
  );

  buffer_full_o <= s_fifo_prog_full;
-
-  -- Transfer write-data-count to read clock domain
-  register_counter_inst : entity work.registerCounter
-    generic map (
-      g_DATA_WIDTH => g_WRITE_COUNTER_WIDTH)
-    port map (
-    clk_input_i => clk_4x_logic_i,
-    data_i      => s_wr_data_count,
-    data_o      => s_wr_data_count_reg,
-    clk_output_i  => ipbus_clk_i
-    );        
-
-  ----! Calculate the number of words in the FIFO .
-  ---- (only valid if no buffer overflow.)
-  ---- Each input word (64 bits) is the same as two output words (32 bits) so
-  ---- multiply s_wr_data_count by 2 before subraction
-  
-  --! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
-   --s_fifo_fill_level <=  (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
-   --s_fifo_fill_level <= unsigned(s_rd_data_count);
  
 END ARCHITECTURE rtl;

--- a/hdl/common/eventFormatter_rtl.vhd
+++ b/hdl/common/eventFormatter_rtl.vhd
--- a/hdl/common/ipbus_ver.vhd
+++ b/hdl/common/ipbus_ver.vhd
@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is

 begin

-  ipbus_out.ipb_rdata <= X"a5ea" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_rdata <= X"a5ed" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
  ipbus_out.ipb_err <= '0';