Commit 5eb3d86a authored by David Cussans's avatar David Cussans

Moving minitlu firmware to subdirectory

parent e5bcc2ba
Introduction to AIDA FMC Mini-TLU {#mainpage}
=================================
The TLU provides different parts of a Particle Physics Beam-Test
system with the information they need to synchronize data taken with
different detectors. The detectors are also refered to as Devices
Under Test (DUT).
Functions of TLU
----------------
- Trigger.
The TLU can combine signals from detectors in the beam-line ( often
scintillation detectors ) to produce a trigger that is sent to the
different DUT. Each DUT can indicate to the TLU that it is busy and
unable to take any further data.
- Particle Timestamping
The arrival time of every pulse from the beam-detectors is recorded.
- Clock and Synchronization Signals.
The TLU produces clock and synchronization signals that allow the
internal counters of different DUT to be sychronized.
N.B. Not all the functions of the TLU may be used in a given beam-test
system. For example, it is common to only use the Trigger/Busy
function of the TLU.
Firmare Structure
-----------------
The firmware is almost exclusively written in VHDL. The top level
entitity is [top_extphy](top_extphy_struct)
The HDL-Designer package by Mentor graphics has been used to develop
some of the code, mainly the top-level structure. However, is is not
necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
Building Firmware
-----------------
Instructions on building the firmware are found
[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
project new fmc-mtlu
project set family spartan6
project set device xc6slx16
project set package csg324
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
project set "Preferred Language" "VHDL"
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
# xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
# xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
# UCF for TLU with FMC connector wrong way round.
#xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU.ucf
# bug-fixed TLU:
xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU_v1a.ucf
project close
puts "Successfully finished building project file"
project open fmc-mtlu
puts "Regenerating cores"
cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
process run "Synthesize"
process run "Translate"
process run "Map"
process run "Place & Route"
process run "Generate Programming File"
project close
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET package = fgg484
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
include ipbus/firmware/ipbus_core/cfg/file_list
project new fmc-mtlu
project set family spartan6
project set device xc6slx45t
project set package fgg484
project set speed -3
project set "Enable Multi-Threading" "2" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
project set "Enable Multi-Threading" "2" -process "Place & Route"
project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
project set "Preferred Language" "VHDL"
project set "Set SPI Configuration Bus Width spartan6" 4
# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
# Just list files by hand for now. Can't get addfiles.tcl to work.
#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
# IPBus Ethernet for gig_eth_pcs_pma_v11_5
xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
puts "Adding and Regenerating Ethernet cores"
# Add cores for Ethernet
exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
xfile add ipcore_dir/mac_fifo_axi4.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
#cd ..
puts "Adding IPBus files"
# Xilinx ISE setup fragment for ipbus core
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_registers.vhd
xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
#xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
#cd ..
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
# Add user constraints file
xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a.ucf
project close
puts "Successfully finished building project file"
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--! @file dtype_fds.vhdl
--
-------------------------------------------------------------------------------
-- --
-- (c) University of Bristol, High Energy Physics Group --
-- --
-------------------------------------------------------------------------------
--
--
-- This file is part of IPBus.
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
--
-- IPBus is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- IPBus is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
--
--
--! Standard library
library IEEE;
-- Standard logic defintions.
use IEEE.STD_LOGIC_1164.all;
--
-- unit name: dtype_fds
--
--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
--
--
--! @author David.Cussans@bristol.ac.uk
--
--! @date 7/May/2011
--
--! @version 0.1
--
--! @details -- Modified from D-type example in VHDL book.
--! See Xilinx spartan6_scm.pdf
--! Output goes high when input goes high ( asyncnronous to system clock).
--
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
--!
--! <b>Modified by:</b>\n
--! Author: <name>
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--! <date> <initials> <log>\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
-------------------------------------------------------------------------------
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--=============================================================================
--! @file IODELAYCal_FSM_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- UoB , USC
-- --
------------------------------------------------------------------------------- --
--
--! @brief Finite-state machine to control calibration and reset signals to
--! Iserdes, IDelay
--! based on code by Alvaro Dosil\n
--
--! @author Alvaro Dosil
--
--! @date 22/Feb/2014
--
--! @version v0.1
--
--! @details
--
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence\n
--! <another thing to do> \n
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity IODELAYCal_FSM is
port (
clk_i : in std_logic; --! Global clock
startcal_i : in std_logic; --! Start calibration
busy_i : in std_logic; --! Status of the IDELAY component
calibrate_o : out std_logic; --! Calibration signals to IODELAY
reset_o : out std_logic --! Reset to IODELAY component
);
end entity IODELAYCal_FSM;
architecture rtl of IODELAYCal_FSM is
--! Calibration FSM state values
type state_values is (st0, st1, st2, st3);
signal pres_state, next_state: state_values := st0;
signal s_cal_FSM : std_logic := '0'; -- IODELAY reset
signal s_rst_FSM : std_logic := '0'; -- IODELAY reset
begin -- rtl
--! Calibration FSM register
statereg: process(clk_i)
begin
if rising_edge(clk_i) then
pres_state <= next_state; -- Move to next state
end if;
end process statereg;
--! Calibration FSM combinational block
fsm: process(pres_state, startcal_i, busy_i)
begin
next_state <= pres_state;
-- Default values
s_Rst_FSM <= '0';
s_cal_FSM <= '0';
case pres_state is
-- st0 - IDLE
when st0=>
if ( startcal_i = '1') then
next_state <= st1; -- Next state is "st1 - SEND CALIBRATION SIGNAL"
end if;
-- st1 - SEND CALIBRATION SIGNAL
when st1=>
s_cal_FSM <= '1';
next_state <= st2; -- Next state is "st2 - WAIT BUSY = '0'"
-- st2 - WAIT BUSY = '0'
when st2=>
if busy_i = '0' then
next_state <= st3; -- Next state is "st3 - RESET STATE"
end if;
-- st3 - RESET STATE
when st3=>
s_Rst_FSM <= '1';
next_state <= st0; -- Next state is "st0 - IDLE"
end case;
end process fsm;
calibrate_o <= s_cal_FSM;
reset_o <= s_Rst_FSM;
end rtl;
--=============================================================================
--! @file IPBusInterface_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
--
--! @brief \n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:57 11/09/12
--