added WR timecode input and aux clock PLL control signals. Changed SPI core to custom module with hw arbitration of the PLL DAC access

fd_delay_channel_driver: fixed possible FSM hang when the card is disabled during generation of a pulse, implemented new calibration scheme

fd_acam_timestamper: now generates calibration start pulses even if BYPASS=1, extended host read timing to avoid SI problems

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@23 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@22 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d