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FMC DEL 1ns 4cha
Commit 361a3128 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fine_delay_core: added bitbanged I2C master and appropriate control registers

parent c43e9ebc
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hdl/rtl/fd_wbgen2_pkg.vhd
View file @ 361a3128
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Thu Oct 27 17:38:05 2011
-- Created : Mon Oct 31 17:01:02 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -41,6 +41,8 @@ package fd_wbgen2_pkg is
tsbr_c_i : std_logic_vector(27 downto 0);
tsbr_fid_fine_i : std_logic_vector(11 downto 0);
tsbr_fid_seqid_i : std_logic_vector(15 downto 0);
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
rawfifo_wr_req_i : std_logic;
rawfifo_frac_i : std_logic_vector(27 downto 0);
rawfifo_coarse_i : std_logic_vector(27 downto 0);
......@@ -79,6 +81,8 @@ package fd_wbgen2_pkg is
tsbr_c_i => (others => '0'),
tsbr_fid_fine_i => (others => '0'),
tsbr_fid_seqid_i => (others => '0'),
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0',
rawfifo_wr_req_i => '0',
rawfifo_frac_i => (others => '0'),
rawfifo_coarse_i => (others => '0'),
......@@ -133,6 +137,8 @@ package fd_wbgen2_pkg is
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
rawfifo_wr_full_o : std_logic;
dcr1_enable_o : std_logic;
dcr1_mode_o : std_logic;
......@@ -227,6 +233,8 @@ package fd_wbgen2_pkg is
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
rawfifo_wr_full_o => '0',
dcr1_enable_o => '0',
dcr1_mode_o => '0',
......@@ -321,6 +329,8 @@ tmp.tsbr_u_i := left.tsbr_u_i or right.tsbr_u_i;
tmp.tsbr_c_i := left.tsbr_c_i or right.tsbr_c_i;
tmp.tsbr_fid_fine_i := left.tsbr_fid_fine_i or right.tsbr_fid_fine_i;
tmp.tsbr_fid_seqid_i := left.tsbr_fid_seqid_i or right.tsbr_fid_seqid_i;
tmp.i2cr_scl_in_i := left.i2cr_scl_in_i or right.i2cr_scl_in_i;
tmp.i2cr_sda_in_i := left.i2cr_sda_in_i or right.i2cr_sda_in_i;
tmp.rawfifo_wr_req_i := left.rawfifo_wr_req_i or right.rawfifo_wr_req_i;
tmp.rawfifo_frac_i := left.rawfifo_frac_i or right.rawfifo_frac_i;
tmp.rawfifo_coarse_i := left.rawfifo_coarse_i or right.rawfifo_coarse_i;
......
hdl/rtl/fd_wishbone_slave.vhd
View file @ 361a3128
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Thu Oct 27 17:38:05 2011
-- Created : Mon Oct 31 17:01:02 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -205,6 +205,8 @@ signal fd_tsbcr_rst_seq_int_delay : std_logic ;
signal fd_tsbcr_rst_seq_sync0 : std_logic ;
signal fd_tsbcr_rst_seq_sync1 : std_logic ;
signal fd_tsbcr_rst_seq_sync2 : std_logic ;
signal fd_i2cr_scl_out_int : std_logic ;
signal fd_i2cr_sda_out_int : std_logic ;
signal fd_rawfifo_in_int : std_logic_vector(55 downto 0);
signal fd_rawfifo_out_int : std_logic_vector(55 downto 0);
signal fd_rawfifo_rdreq_int : std_logic ;
......@@ -620,6 +622,8 @@ begin
fd_tsbcr_rst_seq_int <= '0';
fd_tsbcr_rst_seq_int_delay <= '0';
advance_rbuf_o <= '0';
fd_i2cr_scl_out_int <= '0';
fd_i2cr_sda_out_int <= '0';
fd_dcr1_enable_int <= '0';
fd_dcr1_mode_int <= '0';
fd_dcr1_pg_arm_lw <= '0';
......@@ -1406,6 +1410,50 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
fd_i2cr_scl_out_int <= wrdata_reg(0);
rddata_reg(1) <= 'X';
fd_i2cr_sda_out_int <= wrdata_reg(1);
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
else
rddata_reg(0) <= fd_i2cr_scl_out_int;
rddata_reg(1) <= fd_i2cr_sda_out_int;
rddata_reg(2) <= regs_i.i2cr_scl_in_i;
rddata_reg(3) <= regs_i.i2cr_sda_in_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
fd_dcr1_enable_int <= wrdata_reg(0);
......@@ -3040,6 +3088,12 @@ begin
-- Cycles Value [in 8 ns ticks]
-- Fine Value [in phase units]
-- Timestamp Sequence ID
-- SCL Line out
regs_o.i2cr_scl_out_o <= fd_i2cr_scl_out_int;
-- SDA Line out
regs_o.i2cr_sda_out_o <= fd_i2cr_sda_out_int;
-- SCL Line in
-- SDA Line in
-- extra code for reg/fifo/mem: RAW FIFO
fd_rawfifo_in_int(27 downto 0) <= regs_i.rawfifo_frac_i;
fd_rawfifo_in_int(55 downto 28) <= regs_i.rawfifo_coarse_i;
......
hdl/rtl/fd_wishbone_slave.wb
View file @ 361a3128
......@@ -573,6 +573,39 @@ peripheral {
};
};
reg {
name = "I2C bitbanged IO register";
prefix = "I2CR";
field {
name = "SCL Line out";
prefix = "SCL_OUT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SDA Line out";
prefix = "SDA_OUT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SCL Line in";
prefix = "SCL_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "SDA Line in";
prefix = "SDA_IN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
fifo_reg {
direction = CORE_TO_BUS;
size = 256;
......
hdl/rtl/fine_delay_core.vhd
View file @ 361a3128
......@@ -380,8 +380,8 @@ architecture rtl of fine_delay_core is
signal chx_delay_load : std_logic_vector(3 downto 0);
signal chx_delay_load_done : std_logic_vector(3 downto 0);
signal fan_out : t_wishbone_master_out_array(0 to 2);
signal fan_in : t_wishbone_master_in_array(0 to 2);
signal fan_out : t_wishbone_master_out_array(0 to 1);
signal fan_in : t_wishbone_master_in_array(0 to 1);
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
......@@ -405,10 +405,11 @@ architecture rtl of fine_delay_core is
signal cal_pulse_trigger : std_logic;
signal tm_dac_val_int : std_logic_vector(31 downto 0);
begin -- rtl
wb_in.adr(7 downto 0) <= wb_adr_i;
wb_in.cyc <= wb_cyc_i;
wb_in.stb <= wb_stb_i;
......@@ -421,9 +422,10 @@ begin -- rtl
tm_dac_val_int <= x"00" & tm_dac_value_i;
U_WB_Fanout : xwb_bus_fanout
generic map (
g_num_outputs => 3,
g_num_outputs => 2,
g_bits_per_slave => 6)
port map (
clk_sys_i => clk_sys_i,
......@@ -458,27 +460,12 @@ begin -- rtl
regs_o => regs_towb_csync);
regs_towb_local.gcr_wr_locked_i <= tm_clk_aux_locked_i;
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
U_I2C_Master : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(1),
slave_o => fan_in(1),
scl_pad_o => i2c_scl_o,
scl_padoen_o => i2c_scl_oen_o,
scl_pad_i => i2c_scl_i,
sda_pad_o => i2c_sda_o,
sda_padoen_o => i2c_sda_oen_o,
sda_pad_i => i2c_sda_i);
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o and tm_time_valid_i;
U_SPI_Arbiter : fd_spi_dac_arbiter
generic map (
g_div_ratio_log2 => 4)
g_div_ratio_log2 => 3)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
......@@ -501,8 +488,8 @@ begin -- rtl
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(2),
slave_o => fan_in(2),
slave_i => fan_out(1),
slave_o => fan_in(1),
desc_o => open,
owr_pwren_o => open,
owr_en_o => owr_en_int,
......@@ -511,7 +498,6 @@ begin -- rtl
owr_en_o <= owr_en_int(0);
owr_int(0) <= owr_i;
regs_towb <= regs_towb_csync or regs_towb_tsu or regs_towb_rbuf or regs_towb_local or regs_towb_spi;
U_Wishbone_Slave : fd_wishbone_slave
......@@ -850,4 +836,14 @@ begin -- rtl
delay_pulse_o <= chx_delay_pulse;
i2c_scl_o <='0';
i2c_scl_oen_o <= regs_fromwb.i2cr_scl_out_o;
i2c_sda_o <='0';
i2c_sda_oen_o <= regs_fromwb.i2cr_sda_out_o;
regs_towb_local.i2cr_sda_in_i <= i2c_sda_i;
regs_towb_local.i2cr_scl_in_i <= i2c_scl_i;
end rtl;
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