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FMC DEL 1ns 4cha
Commit 2908b258 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fd_wishbone_slave: added new calibration registers

parent 5094074c
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Showing with 837 additions and 634 deletions
hdl/rtl/fd_wbgen2_pkg.vhd
View file @ 2908b258
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Wed Sep 7 17:10:37 2011
-- Created : Mon Oct 24 13:42:09 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -104,10 +104,13 @@ package fd_wbgen2_pkg is
tar_addr_o : std_logic_vector(3 downto 0);
tdcsr_write_o : std_logic;
tdcsr_read_o : std_logic;
tdcsr_stop_en_o : std_logic;
tdcsr_start_dis_o : std_logic;
tdcsr_start_en_o : std_logic;
tdcsr_stop_dis_o : std_logic;
tdcsr_stop_en_o : std_logic;
tdcsr_alutrig_o : std_logic;
calr_cal_pulse_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
......@@ -122,7 +125,7 @@ package fd_wbgen2_pkg is
dcr1_pg_arm_o : std_logic;
dcr1_pg_arm_load_o : std_logic;
dcr1_update_o : std_logic;
dcr1_force_cp_o : std_logic;
dcr1_force_dly_o : std_logic;
dcr1_pol_o : std_logic;
frr1_o : std_logic_vector(9 downto 0);
u_start1_o : std_logic_vector(31 downto 0);
......@@ -136,7 +139,7 @@ package fd_wbgen2_pkg is
dcr2_pg_arm_o : std_logic;
dcr2_pg_arm_load_o : std_logic;
dcr2_update_o : std_logic;
dcr2_force_cp_o : std_logic;
dcr2_force_dly_o : std_logic;
dcr2_pol_o : std_logic;
frr2_o : std_logic_vector(9 downto 0);
u_start2_o : std_logic_vector(31 downto 0);
......@@ -150,7 +153,7 @@ package fd_wbgen2_pkg is
dcr3_pg_arm_o : std_logic;
dcr3_pg_arm_load_o : std_logic;
dcr3_update_o : std_logic;
dcr3_force_cp_o : std_logic;
dcr3_force_dly_o : std_logic;
dcr3_pol_o : std_logic;
frr3_o : std_logic_vector(9 downto 0);
u_start3_o : std_logic_vector(31 downto 0);
......@@ -164,7 +167,7 @@ package fd_wbgen2_pkg is
dcr4_pg_arm_o : std_logic;
dcr4_pg_arm_load_o : std_logic;
dcr4_update_o : std_logic;
dcr4_force_cp_o : std_logic;
dcr4_force_dly_o : std_logic;
dcr4_pol_o : std_logic;
frr4_o : std_logic_vector(9 downto 0);
u_start4_o : std_logic_vector(31 downto 0);
......@@ -187,10 +190,13 @@ package fd_wbgen2_pkg is
tar_addr_o => (others => '0'),
tdcsr_write_o => '0',
tdcsr_read_o => '0',
tdcsr_stop_en_o => '0',
tdcsr_start_dis_o => '0',
tdcsr_start_en_o => '0',
tdcsr_stop_dis_o => '0',
tdcsr_stop_en_o => '0',
tdcsr_alutrig_o => '0',
calr_cal_pulse_o => '0',
calr_psel_o => (others => '0'),
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
......@@ -205,7 +211,7 @@ package fd_wbgen2_pkg is
dcr1_pg_arm_o => '0',
dcr1_pg_arm_load_o => '0',
dcr1_update_o => '0',
dcr1_force_cp_o => '0',
dcr1_force_dly_o => '0',
dcr1_pol_o => '0',
frr1_o => (others => '0'),
u_start1_o => (others => '0'),
......@@ -219,7 +225,7 @@ package fd_wbgen2_pkg is
dcr2_pg_arm_o => '0',
dcr2_pg_arm_load_o => '0',
dcr2_update_o => '0',
dcr2_force_cp_o => '0',
dcr2_force_dly_o => '0',
dcr2_pol_o => '0',
frr2_o => (others => '0'),
u_start2_o => (others => '0'),
......@@ -233,7 +239,7 @@ package fd_wbgen2_pkg is
dcr3_pg_arm_o => '0',
dcr3_pg_arm_load_o => '0',
dcr3_update_o => '0',
dcr3_force_cp_o => '0',
dcr3_force_dly_o => '0',
dcr3_pol_o => '0',
frr3_o => (others => '0'),
u_start3_o => (others => '0'),
......@@ -247,7 +253,7 @@ package fd_wbgen2_pkg is
dcr4_pg_arm_o => '0',
dcr4_pg_arm_load_o => '0',
dcr4_update_o => '0',
dcr4_force_cp_o => '0',
dcr4_force_dly_o => '0',
dcr4_pol_o => '0',
frr4_o => (others => '0'),
u_start4_o => (others => '0'),
......
hdl/rtl/fd_wishbone_slave.vhd
View file @ 2908b258
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hdl/rtl/fd_wishbone_slave.wb
View file @ 2908b258
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