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FMC DEL 1ns 4cha
Commit 3e17d062 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha

parents cc9cdb55 de052457
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hdl/.gitignore
View file @ 3e17d062
......@@ -8,5 +8,7 @@ modelsim.ini
*.vstf
work
*.bak
hdl/syn/spec_1_1/*
syn/spec_1_1/*
syn/spec_wr_demo/*
syn/tests
transcript
\ No newline at end of file
hdl/include/fine_delay_regs.v
View file @ 3e17d062
......@@ -11,6 +11,10 @@
`define FD_GCR_CSYNC_WR 32'h00000008
`define FD_GCR_WR_READY_OFFSET 4
`define FD_GCR_WR_READY 32'h00000010
`define FD_GCR_WR_LOCK_EN_OFFSET 5
`define FD_GCR_WR_LOCK_EN 32'h00000020
`define FD_GCR_WR_LOCKED_OFFSET 6
`define FD_GCR_WR_LOCKED 32'h00000040
`define ADDR_FD_TAR 8'hc
`define FD_TAR_DATA_OFFSET 0
`define FD_TAR_DATA 32'h0fffffff
......@@ -29,33 +33,55 @@
`define FD_TDCSR_LOAD 32'h00000010
`define FD_TDCSR_EMPTY_OFFSET 5
`define FD_TDCSR_EMPTY 32'h00000020
`define FD_TDCSR_START_DIS_OFFSET 6
`define FD_TDCSR_START_DIS 32'h00000040
`define FD_TDCSR_START_EN_OFFSET 7
`define FD_TDCSR_START_EN 32'h00000080
`define FD_TDCSR_STOP_DIS_OFFSET 8
`define FD_TDCSR_STOP_DIS 32'h00000100
`define FD_TDCSR_STOP_EN_OFFSET 9
`define FD_TDCSR_STOP_EN 32'h00000200
`define ADDR_FD_ADSFR 8'h14
`define ADDR_FD_ATMCR 8'h18
`define FD_TDCSR_STOP_EN_OFFSET 6
`define FD_TDCSR_STOP_EN 32'h00000040
`define FD_TDCSR_START_DIS_OFFSET 7
`define FD_TDCSR_START_DIS 32'h00000080
`define FD_TDCSR_START_EN_OFFSET 8
`define FD_TDCSR_START_EN 32'h00000100
`define FD_TDCSR_STOP_DIS_OFFSET 9
`define FD_TDCSR_STOP_DIS 32'h00000200
`define FD_TDCSR_ALUTRIG_OFFSET 10
`define FD_TDCSR_ALUTRIG 32'h00000400
`define ADDR_FD_CALR 8'h14
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
`define FD_CALR_PSEL_OFFSET 1
`define FD_CALR_PSEL 32'h0000001e
`define ADDR_FD_ADSFR 8'h18
`define ADDR_FD_ATMCR 8'h1c
`define FD_ATMCR_C_THR_OFFSET 0
`define FD_ATMCR_C_THR 32'h0000000f
`define FD_ATMCR_F_THR_OFFSET 4
`define FD_ATMCR_F_THR 32'h07fffff0
`define ADDR_FD_ASOR 8'h1c
`define ADDR_FD_ASOR 8'h20
`define FD_ASOR_OFFSET_OFFSET 0
`define FD_ASOR_OFFSET 32'h007fffff
`define ADDR_FD_IECRAW 8'h20
`define ADDR_FD_IECTAG 8'h24
`define ADDR_FD_IEPD 8'h28
`define ADDR_FD_IECRAW 8'h24
`define ADDR_FD_IECTAG 8'h28
`define ADDR_FD_IEPD 8'h2c
`define FD_IEPD_RST_STAT_OFFSET 0
`define FD_IEPD_RST_STAT 32'h00000001
`define FD_IEPD_PDELAY_OFFSET 1
`define FD_IEPD_PDELAY 32'h000001fe
`define ADDR_FD_RCRR 8'h2c
`define ADDR_FD_RCFR 8'h30
`define ADDR_FD_TSBCR 8'h34
`define ADDR_FD_SCR 8'h30
`define FD_SCR_DATA_OFFSET 0
`define FD_SCR_DATA 32'h00ffffff
`define FD_SCR_SEL_DAC_OFFSET 24
`define FD_SCR_SEL_DAC 32'h01000000
`define FD_SCR_SEL_PLL_OFFSET 25
`define FD_SCR_SEL_PLL 32'h02000000
`define FD_SCR_SEL_GPIO_OFFSET 26
`define FD_SCR_SEL_GPIO 32'h04000000
`define FD_SCR_READY_OFFSET 27
`define FD_SCR_READY 32'h08000000
`define FD_SCR_CPOL_OFFSET 28
`define FD_SCR_CPOL 32'h10000000
`define FD_SCR_START_OFFSET 29
`define FD_SCR_START 32'h20000000
`define ADDR_FD_RCRR 8'h34
`define ADDR_FD_RCFR 8'h38
`define ADDR_FD_TSBCR 8'h3c
`define FD_TSBCR_ENABLE_OFFSET 0
`define FD_TSBCR_ENABLE 32'h00000001
`define FD_TSBCR_PURGE_OFFSET 1
......@@ -66,9 +92,9 @@
`define FD_TSBCR_FULL 32'h00000008
`define FD_TSBCR_EMPTY_OFFSET 4
`define FD_TSBCR_EMPTY 32'h00000010
`define ADDR_FD_TSBR_U 8'h38
`define ADDR_FD_TSBR_C 8'h3c
`define ADDR_FD_TSBR_FID 8'h40
`define ADDR_FD_TSBR_U 8'h40
`define ADDR_FD_TSBR_C 8'h44
`define ADDR_FD_TSBR_FID 8'h48
`define FD_TSBR_FID_FINE_OFFSET 0
`define FD_TSBR_FID_FINE 32'h00000fff
`define FD_TSBR_FID_SEQID_OFFSET 16
......@@ -86,8 +112,8 @@
`define FD_DCR1_UPDATE 32'h00000010
`define FD_DCR1_UPD_DONE_OFFSET 5
`define FD_DCR1_UPD_DONE 32'h00000020
`define FD_DCR1_FORCE_CP_OFFSET 6
`define FD_DCR1_FORCE_CP 32'h00000040
`define FD_DCR1_FORCE_DLY_OFFSET 6
`define FD_DCR1_FORCE_DLY 32'h00000040
`define FD_DCR1_POL_OFFSET 7
`define FD_DCR1_POL 32'h00000080
`define ADDR_FD_FRR1 8'h64
......@@ -110,8 +136,8 @@
`define FD_DCR2_UPDATE 32'h00000010
`define FD_DCR2_UPD_DONE_OFFSET 5
`define FD_DCR2_UPD_DONE 32'h00000020
`define FD_DCR2_FORCE_CP_OFFSET 6
`define FD_DCR2_FORCE_CP 32'h00000040
`define FD_DCR2_FORCE_DLY_OFFSET 6
`define FD_DCR2_FORCE_DLY 32'h00000040
`define FD_DCR2_POL_OFFSET 7
`define FD_DCR2_POL 32'h00000080
`define ADDR_FD_FRR2 8'h84
......@@ -134,8 +160,8 @@
`define FD_DCR3_UPDATE 32'h00000010
`define FD_DCR3_UPD_DONE_OFFSET 5
`define FD_DCR3_UPD_DONE 32'h00000020
`define FD_DCR3_FORCE_CP_OFFSET 6
`define FD_DCR3_FORCE_CP 32'h00000040
`define FD_DCR3_FORCE_DLY_OFFSET 6
`define FD_DCR3_FORCE_DLY 32'h00000040
`define FD_DCR3_POL_OFFSET 7
`define FD_DCR3_POL 32'h00000080
`define ADDR_FD_FRR3 8'ha4
......@@ -158,8 +184,8 @@
`define FD_DCR4_UPDATE 32'h00000010
`define FD_DCR4_UPD_DONE_OFFSET 5
`define FD_DCR4_UPD_DONE 32'h00000020
`define FD_DCR4_FORCE_CP_OFFSET 6
`define FD_DCR4_FORCE_CP 32'h00000040
`define FD_DCR4_FORCE_DLY_OFFSET 6
`define FD_DCR4_FORCE_DLY 32'h00000040
`define FD_DCR4_POL_OFFSET 7
`define FD_DCR4_POL 32'h00000080
`define ADDR_FD_FRR4 8'hc4
......
hdl/rtl/Manifest.py
View file @ 3e17d062
......@@ -20,7 +20,6 @@ fetchto = "../ip_cores"
modules = {
"git" : [
"git@ohwr.org:hdl-core-lib/wr-cores.git",
"git@ohwr.org:hdl-core-lib/general-cores.git" ],
"git@ohwr.org:hdl-core-lib/general-cores.git::wishbone_with_adapter" ],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
};
hdl/rtl/fd_acam_timestamp_postprocessor.vhd
View file @ 3e17d062
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2011-10-20
-- Last update: 2011-10-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -96,7 +96,7 @@ architecture behavioral of fd_acam_timestamp_postprocessor is
-- timestamp
constant c_SCALER_SHIFT : integer := 12;
signal pp_pipe : std_logic_vector(3 downto 0);
signal pp_pipe : std_logic_vector(4 downto 0);
signal post_tag_coarse : unsigned(27 downto 0);
signal post_tag_frac : unsigned(g_frac_bits-1 downto 0);
......@@ -159,28 +159,31 @@ begin -- behavioral
-- rescale the fractional part to our internal time base
pp_pipe(2) <= pp_pipe(1);
--post_frac_multiplied <= resize(signed(post_frac_start_adj) * signed(regs_i.adsfr_o), post_frac_multiplied'length);
-- post_frac_multiplied_d0 <= post_frac_multiplied;
post_frac_multiplied <= resize(signed(post_frac_start_adj) * adsfr_d0, post_frac_multiplied'length);
-- pipeline stage 4: pass the multiplication result through another register
-- (timing improvement)
pp_pipe(3) <= pp_pipe(2);
post_frac_multiplied_d0 <= post_frac_multiplied;
-- pipeline stage 4:
-- - split the rescaled fractional part into the (mod 4096) tag_frac_o and add
-- the rest to the coarse part, along with the start-to-timescale offset
pp_pipe(3) <= pp_pipe(2);
pp_pipe(4) <= pp_pipe(3);
tag_utc_o <= std_logic_vector(post_tag_utc);
tag_coarse_o <= std_logic_vector(
signed(post_tag_coarse) -- index of start pulse (mod 16 = 0)
+ signed(acam_subcycle_offset_i) -- start-to-timescale offset
+ signed(post_frac_multiplied(post_frac_multiplied'left downto c_SCALER_SHIFT + g_frac_bits)));
+ signed(post_frac_multiplied_d0(post_frac_multiplied_d0'left downto c_SCALER_SHIFT + g_frac_bits)));
-- extra coarse counts from ACAM's frac part after rescaling
tag_frac_o <= std_logic_vector(post_frac_multiplied(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_frac_o <= std_logic_vector(post_frac_multiplied_d0(c_SCALER_SHIFT + g_frac_bits-1 downto c_SCALER_SHIFT));
tag_valid_o <= pp_pipe(3);
tag_valid_o <= pp_pipe(4);
end if;
end if;
......
hdl/rtl/fd_spi_master.vhd
View file @ 3e17d062
......@@ -40,137 +40,110 @@ architecture behavioral of fd_spi_master is
signal busy : std_logic;
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(23 downto 0);
signal bitCounter : std_logic_vector(25 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider : unsigned(11 downto 0);
signal divider_muxed : std_logic;
signal cs_sel_dac : std_logic;
signal cs_sel_gpio : std_logic;
signal cs_sel_pll : std_logic;
signal sreg : std_logic_vector(23 downto 0);
signal rx_sreg : std_logic_vector(23 downto 0);
-- signal data_in_reg : std_logic_vector(23 downto 0);
signal data_out_reg : std_logic_vector(23 downto 0);
begin -- rtl
type t_state is (IDLE, TX_CS, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
divider_muxed <= divider(g_div_ratio_log2); -- sclk = clk_i/64
iValidValue <= start_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
begin -- rtl
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' then
if rst_n_i = '0' then
divider <= (others => '0');
elsif sendingData = '1' then
if(divider_muxed = '1') then
else
if(start_i = '1' or divider_muxed = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (others => '0');
end if;
end if;
end process;
divider_muxed <= divider(g_div_ratio_log2); -- sclk = clk_i/64
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
state <= IDLE;
sclk <= '0';
spi_cs_gpio_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_dac_n_o <= '1';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
counter <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_dac <= sel_dac_i;
cs_sel_gpio <= sel_gpio_i;
cs_sel_pll <= sel_pll_i;
dataSh <= data_i; --data_in_reg;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= spi_miso_i; --dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
case state is
when IDLE =>
sclk <= '1';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_cs_dac_n_o <= not sel_dac_i;
spi_cs_pll_n_o <= not sel_pll_i;
spi_cs_gpio_n_o <= not sel_gpio_i;
spi_mosi_o <= data_i(sreg'high);
end if;
when TX_CS =>
if divider_muxed = '1' then
state <= TX_SCK1;
end if;
when TX_SCK1 =>
if(divider_muxed = '1') then
sclk <= not sclk;
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
counter <= counter + 1;
state <= TX_SCK2;
end if;
when TX_SCK2 =>
if(divider_muxed = '1') then
sclk <= not sclk;
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
if(counter = 24) then
state <= TX_CS2;
else
state <= TX_SCK1;
end if;
end if;
when TX_CS2 =>
if(divider_muxed = '1') then
state <= TX_GAP;
spi_cs_gpio_n_o <= '1';
spi_cs_pll_n_o <= '1';
spi_cs_dac_n_o <= '1';
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (divider_muxed = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
ready_o <= not SendingData;
data_o <= dataSh;
spi_mosi_o <= dataSh(dataSh'left);
spi_cs_pll_n_o <= not(sendingData) or (not cs_sel_pll);
spi_cs_dac_n_o <= not(sendingData) or (not cs_sel_dac);
spi_cs_gpio_n_o <= not(sendingData) or (not cs_sel_gpio);
p_drive_sclk : process(iDacClk, cpol_i)
begin
if(cpol_i = '0') then
spi_sclk_o <= (iDacClk);
else
spi_sclk_o <= not (iDacClk);
end if;
end process;
ready_o <= '1' when state = IDLE else '0';
spi_sclk_o <= sclk xor cpol_i;
end behavioral;
hdl/rtl/fine_delay_core.vhd
View file @ 3e17d062
......@@ -103,7 +103,7 @@ entity fine_delay_core is
tm_utc_i : in std_logic_vector(39 downto 0);
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic;
tm_dac_value_i : in std_logic_vector(31 downto 0);
tm_dac_value_i : in std_logic_vector(23 downto 0);
tm_dac_wr_i : in std_logic;
---------------------------------------------------------------------------
......@@ -113,6 +113,14 @@ entity fine_delay_core is
owr_en_o : out std_logic;
owr_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
---------------------------------------------------------------------------
-- Wishbone (classic)
---------------------------------------------------------------------------
......@@ -339,7 +347,7 @@ architecture rtl of fine_delay_core is
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end component;
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(27 downto 0);
signal tag_utc : std_logic_vector(31 downto 0);
......@@ -380,7 +388,7 @@ architecture rtl of fine_delay_core is
signal regs_fromwb : t_fd_out_registers;
signal regs_towb_csync : t_fd_in_registers;
signal regs_towb_spi : t_fd_in_registers;
signal regs_towb_spi : t_fd_in_registers;
signal regs_towb_tsu : t_fd_in_registers;
signal regs_towb_rbuf : t_fd_in_registers;
signal regs_towb_local : t_fd_in_registers := c_fd_in_registers_init_value;
......@@ -395,6 +403,9 @@ architecture rtl of fine_delay_core is
signal gen_cal_pulse : std_logic_vector(3 downto 0);
signal cal_pulse_mask : std_logic_vector(3 downto 0);
signal cal_pulse_trigger : std_logic;
signal tm_dac_val_int : std_logic_vector(31 downto 0);
begin -- rtl
......@@ -408,6 +419,7 @@ begin -- rtl
wb_ack_o <= wb_out.ack;
wb_dat_o <= wb_out.dat;
tm_dac_val_int <= x"00" & tm_dac_value_i;
U_WB_Fanout : xwb_bus_fanout
generic map (
......@@ -446,36 +458,31 @@ begin -- rtl
regs_o => regs_towb_csync);
regs_towb_local.gcr_wr_locked_i <= tm_clk_aux_locked_i;
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
--U_SPI_Master : xwb_spi
-- generic map (
-- g_interface_mode => CLASSIC)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_n_i => rst_n_i,
-- slave_i => fan_out(1),
-- slave_o => fan_in(1),
-- pad_cs_o => spi_cs_vec,
-- pad_sclk_o => spi_sclk_o,
-- pad_mosi_o => spi_mosi_o,
-- pad_miso_i => spi_miso_i);
--spi_cs_dac_n_o <= spi_cs_vec(0);
--spi_cs_pll_n_o <= spi_cs_vec(1);
--spi_cs_gpio_n_o <= spi_cs_vec(2);
fan_in(1).ack <= '1';
fan_in(1).err <= '0';
fan_in(1).rty <= '0';
U_SPI_Arbiter: fd_spi_dac_arbiter
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
U_I2C_Master : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(1),
slave_o => fan_in(1),
scl_pad_o => i2c_scl_o,
scl_padoen_o => i2c_scl_oen_o,
scl_pad_i => i2c_scl_i,
sda_pad_o => i2c_sda_o,
sda_padoen_o => i2c_sda_oen_o,
sda_pad_i => i2c_sda_i);
U_SPI_Arbiter : fd_spi_dac_arbiter
generic map (
g_div_ratio_log2 => 10)
g_div_ratio_log2 => 4)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
tm_dac_value_i => tm_dac_value_i,
tm_dac_value_i => tm_dac_val_int,
tm_dac_wr_i => tm_dac_wr_i,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
......@@ -485,7 +492,7 @@ begin -- rtl
spi_miso_i => spi_miso_i,
regs_i => regs_fromwb,
regs_o => regs_towb_spi);
U_Onewire : xwb_onewire_master
generic map (
......
hdl/syn/spec_1_1/Makefile deleted 100644 → 0
View file @ cc9cdb55
This diff is collapsed.
hdl/syn/spec_1_1/finedelay_spec_1_1.xise deleted 100644 → 0
View file @ cc9cdb55
This diff is collapsed.
hdl/syn/spec_1_1/spec_fine_delay.xise
View file @ 3e17d062
This diff is collapsed.
hdl/testbench/top/Makefile
View file @ 3e17d062
This diff is collapsed.
hdl/testbench/top/main.sv
View file @ 3e17d062
......@@ -217,7 +217,9 @@ class CSimDrv_FineDelay;
task force_cal_pulse(int channel, int delay_setpoint);
m_acc.write(`ADDR_FD_FRR1 + (channel * 'h20), delay_setpoint);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_CP | `FD_DCR1_POL);
m_acc.write(`ADDR_FD_DCR1 + (channel * 'h20), `FD_DCR1_FORCE_DLY | `FD_DCR1_POL);
m_acc.write(`ADDR_FD_TDCSR, `FD_TDCSR_CAL_PULSE);
endtask // force_cal_pulse
endclass // CSimDrv_FineDelay
......@@ -540,12 +542,12 @@ module main;
fd_drv = new(wb);
fd_drv.init();
fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(0,1, 1000000, 200000);
// fd_drv.config_output(1,1, 1100500, 200000);
// fd_drv.config_output(2,1, 1100900, 200000);
// fd_drv.config_output(3,1, 1110100, 200000);
// fd_drv.force_cal_pulse(0, 100);
fd_drv.force_cal_pulse(0, 100);
// #(320ns);
// fd_drv.force_cal_pulse(0, 200);
......
hdl/testbench/top/wave.do
View file @ 3e17d062
......@@ -4,11 +4,6 @@ add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/trig_a_n_i
add wave -noupdate /main/DUT/delay_pulse_o(0)
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate -expand /main/DUT/U_Acam_TSU/trig_d
add wave -noupdate /main/DUT/U_Acam_TSU/trig_pulse
add wave -noupdate /main/DUT/U_Acam_TSU/tag_enable
add wave -noupdate /main/DUT/trig_cal_o
add wave -noupdate /main/DUT/tdc_start_i
add wave -noupdate /main/DUT/led_trig_o
......@@ -33,7 +28,7 @@ add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/delay_len_o
add wave -noupdate /main/DUT/delay_val_o
add wave -noupdate -expand /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/wr_time_valid_i
add wave -noupdate /main/DUT/wr_coarse_i
add wave -noupdate /main/DUT/wr_utc_i
......@@ -66,6 +61,7 @@ add wave -noupdate /main/DUT/tdc_rearm_p1
add wave -noupdate /main/DUT/tdc_start_p1
add wave -noupdate /main/DUT/dcr_enable_vec
add wave -noupdate /main/DUT/dcr_mode_vec
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate /main/DUT/chx_delay_pulse
add wave -noupdate /main/DUT/chx_delay_value
add wave -noupdate /main/DUT/chx_delay_load
......@@ -83,8 +79,10 @@ add wave -noupdate /main/DUT/regs_towb
add wave -noupdate /main/DUT/spi_cs_vec
add wave -noupdate /main/DUT/owr_en_int
add wave -noupdate /main/DUT/owr_int
add wave -noupdate /main/DUT/dbg
add wave -noupdate /main/DUT/gen_cal_pulse
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8140001510 fs} 0}
WaveRestoreCursors {{Cursor 1} {3716002840 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -99,4 +97,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {16800 ns}
WaveRestoreZoom {3191002840 fs} {4241002840 fs}
hdl/top/spec_1_1/spec_top.vhd
View file @ 3e17d062
......@@ -96,6 +96,7 @@ entity spec_top is
fd_delay_val_o : out std_logic_vector(9 downto 0);
fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
onewire_b : inout std_logic
......@@ -320,48 +321,58 @@ architecture rtl of spec_top is
component fine_delay_core
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
wr_time_valid_i : in std_logic;
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
trig_a_n_i : in std_logic;
trig_cal_o : out std_logic;
tdc_start_i : in std_logic;
acam_a_o : out std_logic_vector(3 downto 0);
acam_d_o : out std_logic_vector(27 downto 0);
acam_d_i : in std_logic_vector(27 downto 0);
acam_d_oen_o : out std_logic;
acam_err_i : in std_logic;
acam_int_i : in std_logic;
acam_emptyf_i : in std_logic;
acam_alutrigger_o : out std_logic;
acam_cs_n_o : out std_logic;
acam_wr_n_o : out std_logic;
acam_rd_n_o : out std_logic;
acam_start_dis_o : out std_logic;
acam_stop_dis_o : out std_logic;
led_trig_o : out std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
delay_len_o : out std_logic_vector(3 downto 0);
delay_val_o : out std_logic_vector(9 downto 0);
delay_pulse_o : out std_logic_vector(3 downto 0);
owr_en_o : out std_logic;
owr_i : in std_logic;
tm_time_valid_i : in std_logic := '0';
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
tm_utc_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic := '0';
tm_dac_value_i : in std_logic_vector(23 downto 0) := x"000000";
tm_dac_wr_i : in std_logic := '0';
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_o : out std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic);
end component;
signal rst_n : std_logic;
......@@ -590,7 +601,6 @@ begin
end if;
end process;
--fd_tdc_oe_n_o <= '1';
......@@ -630,35 +640,19 @@ begin
master_o => cnx_out);
cnx_in(2).int <= '0';
cnx_in(2).ack <= '0';
cnx_in(2).ack <= '1';
cnx_in(2).rty <= '0';
cnx_in(2).err <= '0';
cnx_in(0).int <= '0';
cnx_in(0).ack <= '1';
cnx_in(0).rty <= '0';
cnx_in(0).err <= '0';
U_I2C : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n,
slave_i => cnx_out(0),
slave_o => cnx_in(0),
desc_o => open,
scl_pad_i => scl_pad_in,
scl_pad_o => scl_pad_out,
scl_padoen_o => scl_pad_oen,
sda_pad_i => sda_pad_in,
sda_pad_o => sda_pad_out,
sda_padoen_o => sda_pad_oen);
fmc_scl_b <= scl_pad_out when scl_pad_oen = '0' else 'Z';
fmc_sda_b <= sda_pad_out when sda_pad_oen = '0' else 'Z';
scl_pad_in <= fmc_scl_b;
sda_pad_in <= fmc_sda_b;
U_DELAY_CORE : fine_delay_core
port map (
......@@ -682,9 +676,7 @@ begin
acam_rd_n_o => fd_tdc_rd_n_o,
acam_start_dis_o => fd_tdc_start_dis_o,
acam_stop_dis_o => fd_tdc_stop_dis_o,
wr_time_valid_i => '0',
wr_utc_i => x"00000000",
wr_coarse_i => x"0000000",
tm_time_valid_i=>'0',
spi_cs_dac_n_o => fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fd_spi_cs_gpio_n_o,
......@@ -694,6 +686,12 @@ begin
delay_len_o => fd_delay_len_o,
delay_val_o => fd_delay_val_o,
delay_pulse_o => fd_delay_pulse_o,
i2c_scl_i => fmc_scl_b,
i2c_scl_o => scl_pad_out,
i2c_scl_oen_o => scl_pad_oen,
i2c_sda_i => fmc_sda_b,
i2c_sda_o => sda_pad_out,
i2c_sda_oen_o => sda_pad_oen,
owr_i => onewire_b,
owr_en_o => onewire_en,
wb_adr_i => cnx_out(1).adr(7 downto 0),
......
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