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FMC DEL 1ns 4cha
Commit 407e8dd5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' of ohwr.org:fmc-projects/fmc-delay-1ns-8cha

parents e0ec0747 e4a33f30
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circuit_board/Assembly data/EDA-02267-V2-0.OutJob 0 → 100644
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circuit_board/EDA-02267-V2-0_project.Annotation 0 → 100644
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circuit_board/EDA-02267-V2-0_project.PrjPCB 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.DRL 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.DRR 0 → 100644
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---------------------------------------------------------------------------
NCDrill File Report For: FMC_Delay_1ns_4Cha.PcbDoc 1/21/2011 4:37:06 PM
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : FMC_Delay_1ns_4Cha.TXT
EIA File : FMC_Delay_1ns_4Cha.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 10mil (0.254mm) Round 813 351.79 Inch (8935.35 mm)
T2 39.37mil (1mm) Round 4 280.91 Inch (7135.17 mm)
T3 47.24mil (1.1999mm) Round 5 282.10 Inch (7165.24 mm)
T4 66.93mil (1.70002mm) Round 20 284.80 Inch (7234.04 mm)
T5 106.3mil (2.70002mm) Round 4 289.42 Inch (7351.32 mm)
T6 51.18mil (1.29997mm) Round 2 NPTH 284.23 Inch (7219.39 mm)
---------------------------------------------------------------------------
Totals 848 1773.25 Inch (45040.50 mm)
Total Processing Time (hh:mm:ss) : 00:00:00
circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.EXTREP 0 → 100644
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------------------------------------------------------------------------------------------
Gerber File Extension Report For: FMC_Delay_1ns_4Cha.GBR 1/21/2011 4:37:05 PM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL Top Layer
.GP1 Plane L2 PWR
.GP2 Plane L3 3P3V / 3P3V_TDC
.G1 L4 diff
.GP3 Plane L5 GND
.GBL Bottom Layer
.GTO Top Overlay
.GBO Bottom Overlay
.GTP Top Paste
.GBP Bottom Paste
.GTS Top Solder
.GBS Bottom Solder
.GM1 Mechanical 1
------------------------------------------------------------------------------------------
circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.G1 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GBL 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GBO 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GBP 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GBS 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GM1 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GP1 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GP2 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GP3 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GTL 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GTO 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GTP 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.GTS 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.LDP 0 → 100644
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Layer Pairs Export File for PCB: C:\altium-projects\fmc-delay-1ns-8cha\trunk\circuit_board\fmc-delay-1ns-8cha\Schematics\FMC_Delay_1ns_4Cha.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=fmc_delay_1ns_4cha.txt|LayerPairs=gtl,gbl
circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.LDPPreview 0 → 100644
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SmallImageWidth=106
SmallImageHeight=150
SmallImage=78DAEDD5A18F22311407E0F9DBD16814660D0683C260306B50180C660D0A83C1A0B8FC2679A4D74C6E6F93CDE692FBC49799B6AFAFED6CDFF27C3E8727000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003FEA7ABD7E79CEED761B3E3E3E5EEDC7E3F15BBBF226EE3BF6D8E78ECBE5326AF7F4B7EB65BFF7FBFDD333B6F1DF7596AF3A1E8FC36AB51AD6EBF568BBDDBEDE77BBDDF8CCF86C361BDEDEDE86F7F7F7E170388C71692747C6D34E7CDA9BCD667C8FC446622A5F9CCFE7714EECF7FB575CCD498EF4677CB95C8E6AADCC4F4CFA129FEF97FECC497FFE9ED95BDA79E6EF985CB5875A3B63E9ABFEC454CE8CB7FBCE7BF2643C7DA7D3E99FA8A3BABBD95B1F9373B6F730EDF67EE64C5335D5DEC5C4D51A754F1357B92B7F9E19EFEF777FAFA7EE7DDFD7EEB19F9FB5FBB5A6EAA8E64F7D979FAEA7AA89EACF3DCBF76BEBA1AD85C4E759759167CE9267EE6CCED3D655DDC5AC9DF7E44E5CD569D65E2C1663EDB6F59DF1AAF3DA4B722436F73CEF91F7AAEFE4CD7DC8DCBC674EBE71E5CD5A79CF5A55C3C9379FCF5F67AEBAAE39559359ABF69BDC89CB79D297F989CB5AED77ACB8AACDB46BCE9F6AF4B37A6AEF5772F7FFCF6B3C6BF4FFBFDBF7FA1DA9DA6BD7A89C894F8EA93BDDEFA5AD8FFE0C53BF5153F5537D537594B1DA573F56ED3E67D5DAD47EA66ABEFD96ED6F2CC0FFEA17767D0221
circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.REP 0 → 100644
View file @ 407e8dd5
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.REPPreview 0 → 100644
View file @ 407e8dd5
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.RUL 0 → 100644
View file @ 407e8dd5
DRC Rules Export File for PCB: C:\altium-projects\fmc-delay-1ns-8cha\trunk\circuit_board\fmc-delay-1ns-8cha\Schematics\FMC_Delay_1ns_4Cha.PcbDoc
RuleKind=Clearance|RuleName=Clearance_diff_pairs|Scope=Board|Minimum=6.00
RuleKind=Clearance|RuleName=Clearance_trou|Scope=Board|Minimum=10.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.00
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=6.00
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=ShortCircuit|RuleName=SMA_1|Scope=Board|Allowed=1
RuleKind=Width|RuleName=Width_Pair_Diff|Scope=Board|Minimum=5.00
RuleKind=MinimumAnnularRing|RuleName=Minimum_IAR|Scope=Board|Minimum=8.00
RuleKind=MinimumAnnularRing|RuleName=Minimum_OAR|Scope=Board|Minimum=6.00
circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.TXT 0 → 100644
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circuit_board/Manufacturing/FMC_Delay_1ns_4Cha.apr 0 → 100644
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circuit_board/Manufacturing/Status Report.Txt 0 → 100644
View file @ 407e8dd5
Output: Gerber Files
Type : Gerber
From : PCB Document [FMC_Delay_1ns_4Cha.PcbDoc]
Generated File[FMC_Delay_1ns_4Cha.GTL]
Generated File[FMC_Delay_1ns_4Cha.GP1]
Generated File[FMC_Delay_1ns_4Cha.GP2]
Generated File[FMC_Delay_1ns_4Cha.G1]
Generated File[FMC_Delay_1ns_4Cha.GP3]
Generated File[FMC_Delay_1ns_4Cha.GBL]
Generated File[FMC_Delay_1ns_4Cha.GTO]
Generated File[FMC_Delay_1ns_4Cha.GBO]
Generated File[FMC_Delay_1ns_4Cha.GTP]
Generated File[FMC_Delay_1ns_4Cha.GBP]
Generated File[FMC_Delay_1ns_4Cha.GTS]
Generated File[FMC_Delay_1ns_4Cha.GBS]
Generated File[FMC_Delay_1ns_4Cha.GM1]
Generated File[FMC_Delay_1ns_4Cha.RUL]
Generated File[FMC_Delay_1ns_4Cha.EXTREP]
Generated File[FMC_Delay_1ns_4Cha.REP]
Output: NC Drill Files
Type : NC Drill
From : PCB Document [FMC_Delay_1ns_4Cha.PcbDoc]
Generated File[FMC_Delay_1ns_4Cha.TXT]
Generated File[FMC_Delay_1ns_4Cha.DRL]
Generated File[FMC_Delay_1ns_4Cha.LDP]
Generated File[FMC_Delay_1ns_4Cha.DRR]
Files Generated : 20
Documents Printed : 0
Finished Output Generation At 4:37:06 PM On 1/21/2011
circuit_board/Misc/fine_delay_pins_spec.csv 0 → 100644
View file @ 407e8dd5
"Line","SPEC 1.1 FPGA","FMC Connector","Fine delay v2","I/O Standard"
"CLK1_M2C_N","L22","g3","fd_clk_ref_n_i","LVDS_25"
"CLK1_M2C_P","L20","g2","fd_clk_ref_p_i","LVDS_25"
"LA24_P","W14","h28","fd_delay_len_o[0]","LVCMOS25"
"LA24_N","Y14","h29","fd_delay_len_o[1]","LVCMOS25"
"LA29_N","Y18","g31","fd_delay_len_o[2]","LVCMOS25"
"LA29_P","W17","g30","fd_delay_len_o[3]","LVCMOS25"
"LA21_N","W13","h26","fd_delay_pulse_o[0]","LVCMOS25"
"LA21_P","V13","h25","fd_delay_pulse_o[1]","LVCMOS25"
"LA25_N","U15","g28","fd_delay_pulse_o[2]","LVCMOS25"
"LA25_P","T15","g27","fd_delay_pulse_o[3]","LVCMOS25"
"LA32_N","A20","h38","fd_delay_val_o[0]","LVCMOS25"
"LA32_P","B20","h37","fd_delay_val_o[1]","LVCMOS25"
"LA33_N","A19","g37","fd_delay_val_o[2]","LVCMOS25"
"LA33_P","C19","g36","fd_delay_val_o[3]","LVCMOS25"
"LA30_N","W18","h35","fd_delay_val_o[4]","LVCMOS25"
"LA30_P","V17","h34","fd_delay_val_o[5]","LVCMOS25"
"LA31_N","C18","g34","fd_delay_val_o[6]","LVCMOS25"
"LA31_P","D17","g33","fd_delay_val_o[7]","LVCMOS25"
"LA28_N","W15","h32","fd_delay_val_o[8]","LVCMOS25"
"LA28_P","Y16","h31","fd_delay_val_o[9]","LVCMOS25"
"LA15_P","V11","h19","fd_led_trig_o","LVCMOS25"
"LA23_N","AB16","d24","fd_spi_cs_dac_n_o","LVCMOS25"
"LA20_P","R11","g21","fd_spi_cs_gpio_n_o","LVCMOS25"
"LA26_N","AB17","d27","fd_spi_cs_pll_n_o","LVCMOS25"
"LA27_N","AB18","c27","fd_spi_miso_i","LVCMOS25"
"LA27_P","AA18","c26","fd_spi_mosi_o","LVCMOS25"
"LA26_P","Y17","d26","fd_spi_sclk_o","LVCMOS25"
"LA18_P","T12","c22","fd_tdc_a_o[0]","LVCMOS25"
"LA18_N","U12","c23","fd_tdc_a_o[1]","LVCMOS25"
"LA19_P","Y15","h22","fd_tdc_a_o[2]","LVCMOS25"
"LA19_N","AB15","h23","fd_tdc_a_o[3]","LVCMOS25"
"LA16_P","W12","g18","fd_tdc_alutrigger_o","LVCMOS25"
"LA20_N","T11","g22","fd_tdc_cs_n_o","LVCMOS25"
"LA01_N","AB12","d9","fd_tdc_d_b[0]","LVCMOS25"
"LA04_N","U8","h11","fd_tdc_d_b[1]","LVCMOS25"
"LA08_P","R9","g12","fd_tdc_d_b[10]","LVCMOS25"
"LA08_N","R8","g13","fd_tdc_d_b[11]","LVCMOS25"
"LA05_P","AA6","d11","fd_tdc_d_b[12]","LVCMOS25"
"LA05_N","AB6","d12","fd_tdc_d_b[13]","LVCMOS25"
"LA07_P","U9","h13","fd_tdc_d_b[14]","LVCMOS25"
"LA07_N","V9","h14","fd_tdc_d_b[15]","LVCMOS25"
"LA09_P","Y7","d14","fd_tdc_d_b[16]","LVCMOS25"
"LA09_N","AB7","d15","fd_tdc_d_b[17]","LVCMOS25"
"LA10_P","AA8","c14","fd_tdc_d_b[18]","LVCMOS25"
"LA10_N","AB8","c15","fd_tdc_d_b[19]","LVCMOS25"
"LA01_P","AA12","d8","fd_tdc_d_b[2]","LVCMOS25"
"LA12_P","T10","g15","fd_tdc_d_b[20]","LVCMOS25"
"LA12_N","U10","g16","fd_tdc_d_b[21]","LVCMOS25"
"LA11_P","W10","h16","fd_tdc_d_b[22]","LVCMOS25"
"LA11_N","Y10","h17","fd_tdc_d_b[23]","LVCMOS25"
"LA13_P","Y9","d17","fd_tdc_d_b[24]","LVCMOS25"
"LA13_N","AB9","d18","fd_tdc_d_b[25]","LVCMOS25"
"LA14_P","AA4","c18","fd_tdc_d_b[26]","LVCMOS25"
"LA14_N","AB4","c19","fd_tdc_d_b[27]","LVCMOS25"
"LA04_P","T8","h10","fd_tdc_d_b[3]","LVCMOS25"
"LA03_N","W8","g10","fd_tdc_d_b[4]","LVCMOS25"
"LA03_P","V7","g9","fd_tdc_d_b[5]","LVCMOS25"
"LA02_N","Y6","h8","fd_tdc_d_b[6]","LVCMOS25"
"LA02_P","W6","h7","fd_tdc_d_b[7]","LVCMOS25"
"LA06_P","Y5","c10","fd_tdc_d_b[8]","LVCMOS25"
"LA06_N","AB5","c11","fd_tdc_d_b[9]","LVCMOS25"
"LA16_N","Y12","g19","fd_tdc_emptyf_i","LVCMOS25"
"LA23_P","AA16","d23","fd_tdc_oe_n_o","LVCMOS25"
"LA17_N","AB13","d21","fd_tdc_rd_n_o","LVCMOS25"
"LA22_P","R13","g24","fd_tdc_start_dis_o","LVCMOS25"
"CLK0_M2C_N","F16","h5","fd_tdc_start_n_i","LVDS_25"
"CLK0_M2C_P","E16","h4","fd_tdc_start_p_i","LVDS_25"
"LA22_N","T14","g25","fd_tdc_stop_dis_o","LVCMOS25"
"LA17_P","Y13","d20","fd_tdc_wr_n_o","LVCMOS25"
"LA00_P","Y11","g6","fd_trig_a_i","LVCMOS25"
"LA00_N","AB11","g7","fd_trig_cal_o","LVCMOS25"
"FMC_SCL","F7","c30","fmc_scl_b","LVCMOS33"
"FMC_SDA","F8","c31","fmc_sda_b","LVCMOS33"
"LA15_N","W11","h20","onewire_b","LVCMOS25"
"DP0_C2M_N","A6","c3",,
"PRSNT_M2C_L","AB14","h2",,
"GBTCLK0_M2C_P","A10","d4",,
"GBTCLK0_M2C_N","B10","d5",,
"DP0_C2M_P","B6","c2",,
"DP0_M2C_P","D7","c6",,
"DP0_M2C_N","C7","c7",,
"PG_C2M ","AA14","d1",,
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