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FMC DEL 1ns 4cha
Commit 5598a946 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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added WR timecode input and aux clock PLL control signals. Changed SPI core to… 

added WR timecode input and aux clock PLL control signals. Changed SPI core to custom module with hw arbitration of the PLL DAC access
parent 407e8dd5
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Showing with 555 additions and 148 deletions
hdl/rtl/Manifest.py
View file @ 5598a946
......@@ -11,6 +11,8 @@ files = ["fd_acam_timestamper.vhd",
"fd_delay_line_arbiter.vhd",
"fd_rearm_generator.vhd",
"fd_wishbone_slave.vhd",
"fd_spi_master.vhd",
"fd_spi_dac_arbiter.vhd",
"fine_delay_pkg.vhd",
"fine_delay_core.vhd"];
......
hdl/rtl/build_wb.sh
View file @ 5598a946
#!/bin/bash
~/wbgen2/wishbone-gen/wbgen2 -V fine_delay_wb.vhd -H record -p fd_registers_pkg.vhd -K ../sim/fine_delay_regs.v -s defines -C fd_core.h -D 1.html fine_delay_wb.wb
\ No newline at end of file
~/wbgen2/wishbone-gen/wbgen2 -V fd_wishbone_slave.vhd -H record -p fd_wbgen2_pkg.vhd -K ../include/fine_delay_regs.v -s defines -C fd_core.h -D 1.html fd_wishbone_slave.wb
\ No newline at end of file
hdl/rtl/fd_spi_dac_arbiter.vhd 0 → 100644
View file @ 5598a946
library ieee;
use ieee.std_logic_1164.all;
use work.fd_wbgen2_pkg.all;
entity fd_spi_dac_arbiter is
generic (
g_div_ratio_log2 : integer := 2);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
tm_dac_value_i : in std_logic_vector(31 downto 0);
tm_dac_wr_i : in std_logic;
---------------------------------------------------------------------------
-- SPI Bus
---------------------------------------------------------------------------
-- chip select for VCTCXO DAC
spi_cs_dac_n_o : out std_logic;
-- chip select for AD9516 PLL
spi_cs_pll_n_o : out std_logic;
-- chip select for MCP23S17 GPIO
spi_cs_gpio_n_o : out std_logic;
-- these are obvious
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers
);
end fd_spi_dac_arbiter;
architecture behavioral of fd_spi_dac_arbiter is
component fd_spi_master
generic (
g_div_ratio_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(23 downto 0);
sel_dac_i : in std_logic;
sel_pll_i : in std_logic;
sel_gpio_i : in std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(23 downto 0);
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
signal s_start : std_logic;
signal s_data_in : std_logic_vector(23 downto 0);
signal s_data_out : std_logic_vector(23 downto 0);
signal s_sel_dac : std_logic;
signal s_sel_pll : std_logic;
signal s_sel_gpio : std_logic;
signal s_ready : std_logic;
type t_spi_request is
record
pending : std_logic;
granted : std_logic;
grant : std_logic;
done : std_logic;
data : std_logic_vector(23 downto 0);
sel_pll : std_logic;
sel_dac : std_logic;
sel_gpio : std_logic;
end record;
signal rq_host, rq_pll : t_spi_request;
signal prev_rq : std_logic;
type t_arb_state is (WAIT_RQ, SERVE_RQ);
signal state : t_arb_state;
signal granted : std_logic_vector(1 downto 0);
signal scr_data_in : std_logic_vector(23 downto 0);
begin -- behavioral
p_data_in : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
scr_data_in <= (others => '0');
else
if(regs_i.scr_data_load_o = '1') then
scr_data_in <= regs_i.scr_data_o;
end if;
end if;
end if;
end process;
p_rq_host : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rq_host.pending <= '0';
rq_host.data <= (others => '0');
rq_host.sel_dac <= '0';
rq_host.sel_pll <= '0';
rq_host.sel_gpio <= '0';
regs_o.scr_ready_i <= '1';
regs_o.scr_data_i <= (others => '0');
else
if(regs_i.scr_start_o = '1' and rq_host.pending = '0') then
rq_host.pending <= '1';
rq_host.data <= scr_data_in;
rq_host.sel_pll <= regs_i.scr_sel_pll_o;
rq_host.sel_dac <= regs_i.scr_sel_dac_o;
rq_host.sel_gpio <= regs_i.scr_sel_gpio_o;
regs_o.scr_ready_i <= '0';
regs_o.scr_data_i <= (others => '0');
elsif(rq_host.done = '1') then
regs_o.scr_ready_i <= '1';
regs_o.scr_data_i <= s_data_out;
rq_host.pending <= '0';
end if;
end if;
end if;
end process;
rq_pll.sel_gpio <= '0';
rq_pll.sel_dac <= '1';
rq_pll.sel_pll <= '0';
p_rq_pll : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
rq_pll.pending <= '0';
rq_pll.data <= (others => '0');
else
if(tm_dac_wr_i = '1' and rq_pll.pending = '0') then
rq_pll.pending <= '1';
rq_pll.data <= tm_dac_value_i(23 downto 0);
elsif(rq_pll.done = '1') then
rq_pll.pending <= '0';
end if;
end if;
end if;
end process;
p_grant : process(prev_rq, rq_pll, rq_host)
begin
if(rq_pll.pending = '1' and rq_host.pending = '0') then
rq_pll.grant <= '1' and not rq_pll.done;
rq_host.grant <= '0';
elsif (rq_pll.pending = '0' and rq_host.pending = '1') then
rq_pll.grant <= '0';
rq_host.grant <= '1' and not rq_host.done;
elsif (rq_pll.pending = '1' and rq_host.pending = '1') then
rq_pll.grant <= prev_rq and not rq_pll.done;
rq_host.grant <= not prev_rq and not rq_host.done;
else
rq_pll.grant <= '0';
rq_host.grant <= '0';
end if;
end process;
p_arbitrate : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= WAIT_RQ;
s_start <= '0';
s_data_in <= (others => '0');
s_sel_gpio <= '0';
s_sel_pll <= '0';
s_sel_dac <= '0';
else
case state is
when WAIT_RQ =>
rq_pll.done <= '0';
rq_host.done <= '0';
rq_pll.granted <= rq_pll.grant;
rq_host.granted <= rq_host.grant;
if(rq_pll.grant = '1')then
prev_rq <= '0';
s_start <= '1';
s_data_in <= rq_pll.data;
s_sel_dac <= rq_pll.sel_dac;
s_sel_pll <= rq_pll.sel_pll;
s_sel_gpio <= rq_pll.sel_gpio;
state <= SERVE_RQ;
elsif(rq_host.grant = '1') then
prev_rq <= '1';
s_start <= '1';
s_data_in <= rq_host.data;
s_sel_dac <= rq_host.sel_dac;
s_sel_pll <= rq_host.sel_pll;
s_sel_gpio <= rq_host.sel_gpio;
state <= SERVE_RQ;
end if;
when SERVE_RQ =>
if(s_ready = '1' and s_start = '0') then
state <= WAIT_RQ;
rq_host.done <= rq_host.granted;
rq_pll.done <= rq_pll.granted;
end if;
s_start <= '0';
end case;
end if;
end if;
end process;
U_SPI_Master : fd_spi_master
generic map (
g_div_ratio_log2 => g_div_ratio_log2)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
start_i => s_start,
cpol_i => regs_i.scr_cpol_o,
data_i => s_data_in,
sel_dac_i => s_sel_dac,
sel_pll_i => s_sel_pll,
sel_gpio_i => s_sel_gpio,
ready_o => s_ready,
data_o => s_data_out,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
spi_cs_gpio_n_o => spi_cs_gpio_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i);
end behavioral;
hdl/rtl/fd_spi_master.vhd
View file @ 5598a946
......@@ -2,15 +2,23 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fd_wbgen2_pkg.all;
use work.gencores_pkg.all;
entity fd_spi_master is
generic(
g_div_ratio_log2 : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
start_i : in std_logic;
cpol_i : in std_logic;
data_i : in std_logic_vector(23 downto 0);
sel_dac_i : in std_logic;
sel_pll_i : in std_logic;
sel_gpio_i : in std_logic;
ready_o : out std_logic;
data_o : out std_logic_vector(23 downto 0);
-- chip select for VCTCXO DAC
spi_cs_dac_n_o : out std_logic;
......@@ -23,10 +31,7 @@ entity fd_spi_master is
-- these are obvious
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers
spi_miso_i : in std_logic
);
end fd_spi_master;
......@@ -49,30 +54,20 @@ architecture behavioral of fd_spi_master is
signal cs_sel_gpio : std_logic;
signal cs_sel_pll : std_logic;
signal data_in_reg : std_logic_vector(23 downto 0);
-- signal data_in_reg : std_logic_vector(23 downto 0);
signal data_out_reg : std_logic_vector(23 downto 0);
begin -- rtl
divider_muxed <= divider(1); -- sclk = clk_i/64
divider_muxed <= divider(g_div_ratio_log2); -- sclk = clk_i/64
iValidValue <= regs_i.scr_start_o;
iValidValue <= start_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
data_in_reg <= (others => '0');
elsif(regs_i.scr_data_load_o = '1') then
data_in_reg <= regs_i.scr_data_o;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
sendingData <= '0';
......@@ -129,13 +124,13 @@ begin -- rtl
else
if iValidValue = '1' and sendingData = '0' then
cs_sel_dac <= regs_i.scr_sel_dac_o;
cs_sel_gpio <= regs_i.scr_sel_gpio_o;
cs_sel_pll <= regs_i.scr_sel_pll_o;
cs_sel_dac <= sel_dac_i;
cs_sel_gpio <= sel_gpio_i;
cs_sel_pll <= sel_pll_i;
dataSh <= data_in_reg;
dataSh <= data_i; --data_in_reg;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= spi_miso_i; --dataSh(dataSh'left);
dataSh(0) <= spi_miso_i; --dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
......@@ -159,8 +154,8 @@ begin -- rtl
endSendingData <= bitCounter(bitCounter'left);
regs_o.scr_ready_i <= not SendingData;
regs_o.scr_data_i <= dataSh;
ready_o <= not SendingData;
data_o <= dataSh;
spi_mosi_o <= dataSh(dataSh'left);
......@@ -168,9 +163,9 @@ begin -- rtl
spi_cs_dac_n_o <= not(sendingData) or (not cs_sel_dac);
spi_cs_gpio_n_o <= not(sendingData) or (not cs_sel_gpio);
p_drive_sclk : process(iDacClk, regs_i)
p_drive_sclk : process(iDacClk, cpol_i)
begin
if(regs_i.scr_cpol_o = '0') then
if(cpol_i = '0') then
spi_sclk_o <= (iDacClk);
else
spi_sclk_o <= not (iDacClk);
......
hdl/rtl/fd_wbgen2_pkg.vhd
View file @ 5598a946
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Mon Oct 24 13:42:09 2011
-- Created : Thu Oct 27 17:38:05 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -22,6 +22,7 @@ package fd_wbgen2_pkg is
type t_fd_in_registers is record
gcr_wr_ready_i : std_logic;
gcr_wr_locked_i : std_logic;
tar_data_i : std_logic_vector(27 downto 0);
tdcsr_err_i : std_logic;
tdcsr_int_i : std_logic;
......@@ -30,6 +31,8 @@ package fd_wbgen2_pkg is
iecraw_i : std_logic_vector(31 downto 0);
iectag_i : std_logic_vector(31 downto 0);
iepd_pdelay_i : std_logic_vector(7 downto 0);
scr_data_i : std_logic_vector(23 downto 0);
scr_ready_i : std_logic;
rcrr_i : std_logic_vector(31 downto 0);
rcfr_i : std_logic_vector(31 downto 0);
tsbcr_full_i : std_logic;
......@@ -57,6 +60,7 @@ package fd_wbgen2_pkg is
constant c_fd_in_registers_init_value: t_fd_in_registers := (
gcr_wr_ready_i => '0',
gcr_wr_locked_i => '0',
tar_data_i => (others => '0'),
tdcsr_err_i => '0',
tdcsr_int_i => '0',
......@@ -65,6 +69,8 @@ package fd_wbgen2_pkg is
iecraw_i => (others => '0'),
iectag_i => (others => '0'),
iepd_pdelay_i => (others => '0'),
scr_data_i => (others => '0'),
scr_ready_i => '0',
rcrr_i => (others => '0'),
rcfr_i => (others => '0'),
tsbcr_full_i => '0',
......@@ -99,6 +105,7 @@ package fd_wbgen2_pkg is
gcr_input_en_o : std_logic;
gcr_csync_int_o : std_logic;
gcr_csync_wr_o : std_logic;
gcr_wr_lock_en_o : std_logic;
tar_data_o : std_logic_vector(27 downto 0);
tar_data_load_o : std_logic;
tar_addr_o : std_logic_vector(3 downto 0);
......@@ -116,6 +123,13 @@ package fd_wbgen2_pkg is
atmcr_f_thr_o : std_logic_vector(22 downto 0);
asor_offset_o : std_logic_vector(22 downto 0);
iepd_rst_stat_o : std_logic;
scr_data_o : std_logic_vector(23 downto 0);
scr_data_load_o : std_logic;
scr_sel_dac_o : std_logic;
scr_sel_pll_o : std_logic;
scr_sel_gpio_o : std_logic;
scr_cpol_o : std_logic;
scr_start_o : std_logic;
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
......@@ -185,6 +199,7 @@ package fd_wbgen2_pkg is
gcr_input_en_o => '0',
gcr_csync_int_o => '0',
gcr_csync_wr_o => '0',
gcr_wr_lock_en_o => '0',
tar_data_o => (others => '0'),
tar_data_load_o => '0',
tar_addr_o => (others => '0'),
......@@ -202,6 +217,13 @@ package fd_wbgen2_pkg is
atmcr_f_thr_o => (others => '0'),
asor_offset_o => (others => '0'),
iepd_rst_stat_o => '0',
scr_data_o => (others => '0'),
scr_data_load_o => '0',
scr_sel_dac_o => '0',
scr_sel_pll_o => '0',
scr_sel_gpio_o => '0',
scr_cpol_o => '0',
scr_start_o => '0',
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
......@@ -280,6 +302,7 @@ function "or" (left, right: t_fd_in_registers) return t_fd_in_registers is
variable tmp: t_fd_in_registers;
begin
tmp.gcr_wr_ready_i := left.gcr_wr_ready_i or right.gcr_wr_ready_i;
tmp.gcr_wr_locked_i := left.gcr_wr_locked_i or right.gcr_wr_locked_i;
tmp.tar_data_i := left.tar_data_i or right.tar_data_i;
tmp.tdcsr_err_i := left.tdcsr_err_i or right.tdcsr_err_i;
tmp.tdcsr_int_i := left.tdcsr_int_i or right.tdcsr_int_i;
......@@ -288,6 +311,8 @@ tmp.tdcsr_empty_i := left.tdcsr_empty_i or right.tdcsr_empty_i;
tmp.iecraw_i := left.iecraw_i or right.iecraw_i;
tmp.iectag_i := left.iectag_i or right.iectag_i;
tmp.iepd_pdelay_i := left.iepd_pdelay_i or right.iepd_pdelay_i;
tmp.scr_data_i := left.scr_data_i or right.scr_data_i;
tmp.scr_ready_i := left.scr_ready_i or right.scr_ready_i;
tmp.rcrr_i := left.rcrr_i or right.rcrr_i;
tmp.rcfr_i := left.rcfr_i or right.rcfr_i;
tmp.tsbcr_full_i := left.tsbcr_full_i or right.tsbcr_full_i;
......
hdl/rtl/fd_wishbone_slave.vhd
View file @ 5598a946
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Mon Oct 24 13:42:09 2011
-- Created : Thu Oct 27 17:38:05 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
......@@ -57,8 +57,7 @@ signal fd_gcr_csync_wr_int_delay : std_logic ;
signal fd_gcr_csync_wr_sync0 : std_logic ;
signal fd_gcr_csync_wr_sync1 : std_logic ;
signal fd_gcr_csync_wr_sync2 : std_logic ;
signal fd_gcr_wr_ready_sync0 : std_logic ;
signal fd_gcr_wr_ready_sync1 : std_logic ;
signal fd_gcr_wr_lock_en_int : std_logic ;
signal fd_tar_data_int_read : std_logic_vector(27 downto 0);
signal fd_tar_data_int_write : std_logic_vector(27 downto 0);
signal fd_tar_data_lw : std_logic ;
......@@ -178,6 +177,12 @@ signal fd_iepd_pdelay_lwb_in_progress : std_logic ;
signal fd_iepd_pdelay_lwb_s0 : std_logic ;
signal fd_iepd_pdelay_lwb_s1 : std_logic ;
signal fd_iepd_pdelay_lwb_s2 : std_logic ;
signal fd_scr_sel_dac_int : std_logic ;
signal fd_scr_sel_pll_int : std_logic ;
signal fd_scr_sel_gpio_int : std_logic ;
signal fd_scr_cpol_int : std_logic ;
signal fd_scr_start_dly0 : std_logic ;
signal fd_scr_start_int : std_logic ;
signal fd_rcrr_int : std_logic_vector(31 downto 0);
signal fd_rcrr_lwb : std_logic ;
signal fd_rcrr_lwb_delay : std_logic ;
......@@ -547,6 +552,7 @@ begin
fd_gcr_csync_int_int_delay <= '0';
fd_gcr_csync_wr_int <= '0';
fd_gcr_csync_wr_int_delay <= '0';
fd_gcr_wr_lock_en_int <= '0';
fd_tar_data_lw <= '0';
fd_tar_data_lw_delay <= '0';
fd_tar_data_lw_read_in_progress <= '0';
......@@ -597,6 +603,12 @@ begin
fd_iepd_pdelay_lwb <= '0';
fd_iepd_pdelay_lwb_delay <= '0';
fd_iepd_pdelay_lwb_in_progress <= '0';
regs_o.scr_data_load_o <= '0';
fd_scr_sel_dac_int <= '0';
fd_scr_sel_pll_int <= '0';
fd_scr_sel_gpio_int <= '0';
fd_scr_cpol_int <= '0';
fd_scr_start_int <= '0';
fd_rcrr_lwb <= '0';
fd_rcrr_lwb_delay <= '0';
fd_rcrr_lwb_in_progress <= '0';
......@@ -751,6 +763,8 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.rstr_wr_o <= '0';
regs_o.scr_data_load_o <= '0';
fd_scr_start_int <= '0';
fd_tsbcr_purge_int <= '0';
advance_rbuf_o <= '0';
eic_idr_write_int <= '0';
......@@ -817,6 +831,7 @@ begin
rddata_reg(8 downto 1) <= fd_iepd_pdelay_int;
fd_iepd_pdelay_lwb_in_progress <= '0';
end if;
regs_o.scr_data_load_o <= '0';
fd_rcrr_lwb <= fd_rcrr_lwb_delay;
fd_rcrr_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fd_rcrr_lwb_in_progress = '1')) then
......@@ -990,14 +1005,17 @@ begin
fd_gcr_csync_wr_int <= wrdata_reg(3);
fd_gcr_csync_wr_int_delay <= wrdata_reg(3);
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
fd_gcr_wr_lock_en_int <= wrdata_reg(5);
rddata_reg(6) <= 'X';
else
rddata_reg(0) <= fd_gcr_bypass_int;
rddata_reg(1) <= fd_gcr_input_en_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= fd_gcr_wr_ready_sync1;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(4) <= regs_i.gcr_wr_ready_i;
rddata_reg(5) <= fd_gcr_wr_lock_en_int;
rddata_reg(6) <= regs_i.gcr_wr_locked_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -1266,6 +1284,33 @@ begin
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
regs_o.scr_data_load_o <= '1';
rddata_reg(24) <= 'X';
fd_scr_sel_dac_int <= wrdata_reg(24);
rddata_reg(25) <= 'X';
fd_scr_sel_pll_int <= wrdata_reg(25);
rddata_reg(26) <= 'X';
fd_scr_sel_gpio_int <= wrdata_reg(26);
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
fd_scr_cpol_int <= wrdata_reg(28);
fd_scr_start_int <= wrdata_reg(29);
rddata_reg(29) <= 'X';
else
rddata_reg(23 downto 0) <= regs_i.scr_data_i;
rddata_reg(24) <= fd_scr_sel_dac_int;
rddata_reg(25) <= fd_scr_sel_pll_int;
rddata_reg(26) <= fd_scr_sel_gpio_int;
rddata_reg(27) <= regs_i.scr_ready_i;
rddata_reg(28) <= fd_scr_cpol_int;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
else
fd_rcrr_lwb <= '1';
......@@ -1274,7 +1319,7 @@ begin
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001101" =>
when "001110" =>
if (wb_we_i = '1') then
else
fd_rcfr_lwb <= '1';
......@@ -1283,7 +1328,7 @@ begin
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "001110" =>
when "001111" =>
if (wb_we_i = '1') then
rddata_reg(0) <= 'X';
fd_tsbcr_enable_int <= wrdata_reg(0);
......@@ -1330,14 +1375,14 @@ begin
end if;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001111" =>
when "010000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= regs_i.tsbr_u_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
when "010001" =>
if (wb_we_i = '1') then
else
rddata_reg(27 downto 0) <= regs_i.tsbr_c_i;
......@@ -1348,7 +1393,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
when "010010" =>
if (wb_we_i = '1') then
else
rddata_reg(11 downto 0) <= regs_i.tsbr_fid_fine_i;
......@@ -2471,19 +2516,9 @@ begin
-- White Rabbit Timecode Ready
-- synchronizer chain for field : White Rabbit Timecode Ready (type RO/WO, clk_ref_i -> bus_clock_int)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_gcr_wr_ready_sync0 <= '0';
fd_gcr_wr_ready_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_gcr_wr_ready_sync0 <= regs_i.gcr_wr_ready_i;
fd_gcr_wr_ready_sync1 <= fd_gcr_wr_ready_sync0;
end if;
end process;
-- White Rabbit Locking Enable
regs_o.gcr_wr_lock_en_o <= fd_gcr_wr_lock_en_int;
-- White Rabbit Oscillator Locked
-- DATA
-- asynchronous std_logic_vector register : DATA (type RW/WO, clk_ref_i <-> bus_clock_int)
process (clk_ref_i, rst_n_i)
......@@ -2903,6 +2938,30 @@ begin
end process;
-- Data
regs_o.scr_data_o <= wrdata_reg(23 downto 0);
-- Select DAC
regs_o.scr_sel_dac_o <= fd_scr_sel_dac_int;
-- Select PLL
regs_o.scr_sel_pll_o <= fd_scr_sel_pll_int;
-- Select GPIO
regs_o.scr_sel_gpio_o <= fd_scr_sel_gpio_int;
-- Ready flag
-- Clock Polarity
regs_o.scr_cpol_o <= fd_scr_cpol_int;
-- Transfer Start
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
fd_scr_start_dly0 <= '0';
regs_o.scr_start_o <= '0';
elsif rising_edge(bus_clock_int) then
fd_scr_start_dly0 <= fd_scr_start_int;
regs_o.scr_start_o <= fd_scr_start_int and (not fd_scr_start_dly0);
end if;
end process;
-- Rate
-- asynchronous std_logic_vector register : Rate (type RO/WO, clk_ref_i <-> bus_clock_int)
process (clk_ref_i, rst_n_i)
......
hdl/rtl/fd_wishbone_slave.wb
View file @ 5598a946
......@@ -85,10 +85,30 @@ peripheral {
read 0: WR time code input is invalid. Can't do sounter sync for the moment.";
prefix = "WR_READY";
type = BIT;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "White Rabbit Locking Enable";
description = "write 1: enable locking of the local oscillator to the WR clock.";
prefix = "WR_LOCK_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "White Rabbit Oscillator Locked";
description = "read 1: LO is locked to WR\n 0: LO not locked of free running.";
prefix = "WR_LOCKED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......@@ -349,75 +369,74 @@ peripheral {
};
};
-- reg {
-- name = "SPI Control Register";
-- prefix = "SCR";
-- description = "Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.";
-- field {
-- name = "Data";
-- prefix = "DATA";
-- size = 24;
-- description = "Data to be read/written from/to the SPI bus";
-- type = SLV;
-- load = LOAD_EXT;
-- access_dev = READ_WRITE;
-- access_bus = READ_WRITE;
-- };
reg {
name = "SPI Control Register";
prefix = "SCR";
description = "Single control register for the SPI Controller, allowing for single-cycle (non-waiting) updates of the DAC, GPIO & PLL.";
field {
name = "Data";
prefix = "DATA";
size = 24;
description = "Data to be read/written from/to the SPI bus";
type = SLV;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
-- field {
-- name = "Select DAC";
-- prefix = "SEL_DAC";
-- type = BIT;
-- description = "write 1: selects the DAC as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Select PLL";
-- prefix = "SEL_PLL";
-- type = BIT;
-- description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Select GPIO";
-- prefix = "SEL_GPIO";
-- type = BIT;
-- description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer";
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Ready flag";
-- prefix = "READY";
-- type = BIT;
-- description = "read 0: SPI controller is busy performing a transfer\
-- read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field";
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
-- field {
-- name = "Clock Polarity";
-- description = "0: SPI clock is not inverted\
-- 1: SPI clock is inverted";
-- prefix = "CPOL";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "Transfer Start";
-- prefix = "START";
-- type = MONOSTABLE;
-- description = "write 1: Starts transfer to the selected peripheral\
-- write 0: no effect";
-- };
-- };
field {
name = "Select DAC";
prefix = "SEL_DAC";
type = BIT;
description = "write 1: selects the DAC as the target peripheral of the transfer";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Select PLL";
prefix = "SEL_PLL";
type = BIT;
description = "write 1: selects the AD9516 PLL as the target peripheral of the transfer";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Select GPIO";
prefix = "SEL_GPIO";
type = BIT;
description = "write 1: selects the MCP23S17 GPIO as the target peripheral of the transfer";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Ready flag";
prefix = "READY";
type = BIT;
description = "read 0: SPI controller is busy performing a transfer\
read 1: SPI controller has finished its previous transfer. Read-back data is available in the DATA field";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Clock Polarity";
description = "0: SPI clock is not inverted\
1: SPI clock is inverted";
prefix = "CPOL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transfer Start";
prefix = "START";
type = MONOSTABLE;
description = "write 1: Starts transfer to the selected peripheral\
write 0: no effect";
};
};
reg {
......
hdl/rtl/fine_delay_core.vhd
View file @ 5598a946
......@@ -95,12 +95,16 @@ entity fine_delay_core is
delay_pulse_o : out std_logic_vector(3 downto 0);
---------------------------------------------------------------------------
-- WhiteRabbit time sync
-- WhiteRabbit time/frequency sync
---------------------------------------------------------------------------
wr_time_valid_i : in std_logic;
wr_coarse_i : in std_logic_vector(27 downto 0);
wr_utc_i : in std_logic_vector(31 downto 0);
tm_time_valid_i : in std_logic;
tm_cycles_i : in std_logic_vector(27 downto 0);
tm_utc_i : in std_logic_vector(39 downto 0);
tm_clk_aux_lock_en_o : out std_logic;
tm_clk_aux_locked_i : in std_logic;
tm_dac_value_i : in std_logic_vector(31 downto 0);
tm_dac_wr_i : in std_logic;
---------------------------------------------------------------------------
-- Temeperature sensor (1-wire)
......@@ -318,6 +322,24 @@ architecture rtl of fine_delay_core is
rearm_p1_o : out std_logic);
end component;
component fd_spi_dac_arbiter
generic (
g_div_ratio_log2 : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
tm_dac_value_i : in std_logic_vector(31 downto 0);
tm_dac_wr_i : in std_logic;
spi_cs_dac_n_o : out std_logic;
spi_cs_pll_n_o : out std_logic;
spi_cs_gpio_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
regs_i : in t_fd_out_registers;
regs_o : out t_fd_in_registers);
end component;
signal tag_frac : std_logic_vector(c_TIMESTAMP_FRAC_BITS-1 downto 0);
signal tag_coarse : std_logic_vector(27 downto 0);
signal tag_utc : std_logic_vector(31 downto 0);
......@@ -358,6 +380,7 @@ architecture rtl of fine_delay_core is
signal regs_fromwb : t_fd_out_registers;
signal regs_towb_csync : t_fd_in_registers;
signal regs_towb_spi : t_fd_in_registers;
signal regs_towb_tsu : t_fd_in_registers;
signal regs_towb_rbuf : t_fd_in_registers;
signal regs_towb_local : t_fd_in_registers := c_fd_in_registers_init_value;
......@@ -413,32 +436,56 @@ begin -- rtl
port map (
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_ref,
wr_time_valid_i => wr_time_valid_i,
wr_utc_i => wr_utc_i,
wr_coarse_i => wr_coarse_i,
wr_time_valid_i => tm_time_valid_i,
wr_utc_i => tm_utc_i(31 downto 0),
wr_coarse_i => tm_cycles_i,
csync_p1_o => master_csync_p1,
csync_utc_o => master_csync_utc,
csync_coarse_o => master_csync_coarse,
regs_i => regs_fromwb,
regs_o => regs_towb_csync);
U_SPI_Master : xwb_spi
regs_towb_local.gcr_wr_locked_i <= tm_clk_aux_locked_i;
tm_clk_aux_lock_en_o <= regs_fromwb.gcr_wr_lock_en_o;
--U_SPI_Master : xwb_spi
-- generic map (
-- g_interface_mode => CLASSIC)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_n_i => rst_n_i,
-- slave_i => fan_out(1),
-- slave_o => fan_in(1),
-- pad_cs_o => spi_cs_vec,
-- pad_sclk_o => spi_sclk_o,
-- pad_mosi_o => spi_mosi_o,
-- pad_miso_i => spi_miso_i);
--spi_cs_dac_n_o <= spi_cs_vec(0);
--spi_cs_pll_n_o <= spi_cs_vec(1);
--spi_cs_gpio_n_o <= spi_cs_vec(2);
fan_in(1).ack <= '1';
fan_in(1).err <= '0';
fan_in(1).rty <= '0';
U_SPI_Arbiter: fd_spi_dac_arbiter
generic map (
g_interface_mode => CLASSIC)
g_div_ratio_log2 => 10)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => fan_out(1),
slave_o => fan_in(1),
pad_cs_o => spi_cs_vec,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i);
spi_cs_dac_n_o <= spi_cs_vec(0);
spi_cs_pll_n_o <= spi_cs_vec(1);
spi_cs_gpio_n_o <= spi_cs_vec(2);
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys,
tm_dac_value_i => tm_dac_value_i,
tm_dac_wr_i => tm_dac_wr_i,
spi_cs_dac_n_o => spi_cs_dac_n_o,
spi_cs_pll_n_o => spi_cs_pll_n_o,
spi_cs_gpio_n_o => spi_cs_gpio_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
regs_i => regs_fromwb,
regs_o => regs_towb_spi);
U_Onewire : xwb_onewire_master
generic map (
......@@ -458,7 +505,7 @@ begin -- rtl
owr_int(0) <= owr_i;
regs_towb <= regs_towb_csync or regs_towb_tsu or regs_towb_rbuf or regs_towb_local;
regs_towb <= regs_towb_csync or regs_towb_tsu or regs_towb_rbuf or regs_towb_local or regs_towb_spi;
U_Wishbone_Slave : fd_wishbone_slave
port map (
......
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