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FMC DEL 1ns 4cha
Commit b1394316 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: updated simulation reg definitions

parent 5598a946
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Showing with 54 additions and 28 deletions
hdl/include/fine_delay_regs.v
View file @ b1394316
......@@ -11,6 +11,10 @@
`define FD_GCR_CSYNC_WR 32'h00000008
`define FD_GCR_WR_READY_OFFSET 4
`define FD_GCR_WR_READY 32'h00000010
`define FD_GCR_WR_LOCK_EN_OFFSET 5
`define FD_GCR_WR_LOCK_EN 32'h00000020
`define FD_GCR_WR_LOCKED_OFFSET 6
`define FD_GCR_WR_LOCKED 32'h00000040
`define ADDR_FD_TAR 8'hc
`define FD_TAR_DATA_OFFSET 0
`define FD_TAR_DATA 32'h0fffffff
......@@ -29,33 +33,55 @@
`define FD_TDCSR_LOAD 32'h00000010
`define FD_TDCSR_EMPTY_OFFSET 5
`define FD_TDCSR_EMPTY 32'h00000020
`define FD_TDCSR_START_DIS_OFFSET 6
`define FD_TDCSR_START_DIS 32'h00000040
`define FD_TDCSR_START_EN_OFFSET 7
`define FD_TDCSR_START_EN 32'h00000080
`define FD_TDCSR_STOP_DIS_OFFSET 8
`define FD_TDCSR_STOP_DIS 32'h00000100
`define FD_TDCSR_STOP_EN_OFFSET 9
`define FD_TDCSR_STOP_EN 32'h00000200
`define ADDR_FD_ADSFR 8'h14
`define ADDR_FD_ATMCR 8'h18
`define FD_TDCSR_STOP_EN_OFFSET 6
`define FD_TDCSR_STOP_EN 32'h00000040
`define FD_TDCSR_START_DIS_OFFSET 7
`define FD_TDCSR_START_DIS 32'h00000080
`define FD_TDCSR_START_EN_OFFSET 8
`define FD_TDCSR_START_EN 32'h00000100
`define FD_TDCSR_STOP_DIS_OFFSET 9
`define FD_TDCSR_STOP_DIS 32'h00000200
`define FD_TDCSR_ALUTRIG_OFFSET 10
`define FD_TDCSR_ALUTRIG 32'h00000400
`define ADDR_FD_CALR 8'h14
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
`define FD_CALR_PSEL_OFFSET 1
`define FD_CALR_PSEL 32'h0000001e
`define ADDR_FD_ADSFR 8'h18
`define ADDR_FD_ATMCR 8'h1c
`define FD_ATMCR_C_THR_OFFSET 0
`define FD_ATMCR_C_THR 32'h0000000f
`define FD_ATMCR_F_THR_OFFSET 4
`define FD_ATMCR_F_THR 32'h07fffff0
`define ADDR_FD_ASOR 8'h1c
`define ADDR_FD_ASOR 8'h20
`define FD_ASOR_OFFSET_OFFSET 0
`define FD_ASOR_OFFSET 32'h007fffff
`define ADDR_FD_IECRAW 8'h20
`define ADDR_FD_IECTAG 8'h24
`define ADDR_FD_IEPD 8'h28
`define ADDR_FD_IECRAW 8'h24
`define ADDR_FD_IECTAG 8'h28
`define ADDR_FD_IEPD 8'h2c
`define FD_IEPD_RST_STAT_OFFSET 0
`define FD_IEPD_RST_STAT 32'h00000001
`define FD_IEPD_PDELAY_OFFSET 1
`define FD_IEPD_PDELAY 32'h000001fe
`define ADDR_FD_RCRR 8'h2c
`define ADDR_FD_RCFR 8'h30
`define ADDR_FD_TSBCR 8'h34
`define ADDR_FD_SCR 8'h30
`define FD_SCR_DATA_OFFSET 0
`define FD_SCR_DATA 32'h00ffffff
`define FD_SCR_SEL_DAC_OFFSET 24
`define FD_SCR_SEL_DAC 32'h01000000
`define FD_SCR_SEL_PLL_OFFSET 25
`define FD_SCR_SEL_PLL 32'h02000000
`define FD_SCR_SEL_GPIO_OFFSET 26
`define FD_SCR_SEL_GPIO 32'h04000000
`define FD_SCR_READY_OFFSET 27
`define FD_SCR_READY 32'h08000000
`define FD_SCR_CPOL_OFFSET 28
`define FD_SCR_CPOL 32'h10000000
`define FD_SCR_START_OFFSET 29
`define FD_SCR_START 32'h20000000
`define ADDR_FD_RCRR 8'h34
`define ADDR_FD_RCFR 8'h38
`define ADDR_FD_TSBCR 8'h3c
`define FD_TSBCR_ENABLE_OFFSET 0
`define FD_TSBCR_ENABLE 32'h00000001
`define FD_TSBCR_PURGE_OFFSET 1
......@@ -66,9 +92,9 @@
`define FD_TSBCR_FULL 32'h00000008
`define FD_TSBCR_EMPTY_OFFSET 4
`define FD_TSBCR_EMPTY 32'h00000010
`define ADDR_FD_TSBR_U 8'h38
`define ADDR_FD_TSBR_C 8'h3c
`define ADDR_FD_TSBR_FID 8'h40
`define ADDR_FD_TSBR_U 8'h40
`define ADDR_FD_TSBR_C 8'h44
`define ADDR_FD_TSBR_FID 8'h48
`define FD_TSBR_FID_FINE_OFFSET 0
`define FD_TSBR_FID_FINE 32'h00000fff
`define FD_TSBR_FID_SEQID_OFFSET 16
......@@ -86,8 +112,8 @@
`define FD_DCR1_UPDATE 32'h00000010
`define FD_DCR1_UPD_DONE_OFFSET 5
`define FD_DCR1_UPD_DONE 32'h00000020
`define FD_DCR1_FORCE_CP_OFFSET 6
`define FD_DCR1_FORCE_CP 32'h00000040
`define FD_DCR1_FORCE_DLY_OFFSET 6
`define FD_DCR1_FORCE_DLY 32'h00000040
`define FD_DCR1_POL_OFFSET 7
`define FD_DCR1_POL 32'h00000080
`define ADDR_FD_FRR1 8'h64
......@@ -110,8 +136,8 @@
`define FD_DCR2_UPDATE 32'h00000010
`define FD_DCR2_UPD_DONE_OFFSET 5
`define FD_DCR2_UPD_DONE 32'h00000020
`define FD_DCR2_FORCE_CP_OFFSET 6
`define FD_DCR2_FORCE_CP 32'h00000040
`define FD_DCR2_FORCE_DLY_OFFSET 6
`define FD_DCR2_FORCE_DLY 32'h00000040
`define FD_DCR2_POL_OFFSET 7
`define FD_DCR2_POL 32'h00000080
`define ADDR_FD_FRR2 8'h84
......@@ -134,8 +160,8 @@
`define FD_DCR3_UPDATE 32'h00000010
`define FD_DCR3_UPD_DONE_OFFSET 5
`define FD_DCR3_UPD_DONE 32'h00000020
`define FD_DCR3_FORCE_CP_OFFSET 6
`define FD_DCR3_FORCE_CP 32'h00000040
`define FD_DCR3_FORCE_DLY_OFFSET 6
`define FD_DCR3_FORCE_DLY 32'h00000040
`define FD_DCR3_POL_OFFSET 7
`define FD_DCR3_POL 32'h00000080
`define ADDR_FD_FRR3 8'ha4
......@@ -158,8 +184,8 @@
`define FD_DCR4_UPDATE 32'h00000010
`define FD_DCR4_UPD_DONE_OFFSET 5
`define FD_DCR4_UPD_DONE 32'h00000020
`define FD_DCR4_FORCE_CP_OFFSET 6
`define FD_DCR4_FORCE_CP 32'h00000040
`define FD_DCR4_FORCE_DLY_OFFSET 6
`define FD_DCR4_FORCE_DLY 32'h00000040
`define FD_DCR4_POL_OFFSET 7
`define FD_DCR4_POL 32'h00000080
`define ADDR_FD_FRR4 8'hc4
......
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