- 04 Jul, 2016 5 commits
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Jan Pospisil authored
added trigger latency specification (not implemented yet); renamed some WB registers to better reflect it purpose
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 01 Jul, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
separated registers for delay configuration (for better operability); added basic testbench for "delay configuration"; fixed few bugs around delay configuration; used WBGEN2 generated Verilog constant file for simulation; typos
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Jan Pospisil authored
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- 30 Jun, 2016 3 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 28 Jun, 2016 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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